File: arm64-srl-and.ll

package info (click to toggle)
llvm-toolchain-19 1%3A19.1.7-3
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 1,998,520 kB
  • sloc: cpp: 6,951,680; ansic: 1,486,157; asm: 913,598; python: 232,024; f90: 80,126; objc: 75,281; lisp: 37,276; pascal: 16,990; sh: 10,009; ml: 5,058; perl: 4,724; awk: 3,523; makefile: 3,167; javascript: 2,504; xml: 892; fortran: 664; cs: 573
file content (31 lines) | stat: -rw-r--r-- 869 bytes parent folder | download | duplicates (12) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -O3 < %s | FileCheck %s

; This used to miscompile:
; The 16-bit -1 should not become 32-bit -1 (sub w8, w8, #1).

@g = global i16 0, align 4
define i32 @srl_and()  {
; CHECK-LABEL: srl_and:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    adrp x8, :got:g
; CHECK-NEXT:    mov w9, #50
; CHECK-NEXT:    ldr x8, [x8, :got_lo12:g]
; CHECK-NEXT:    ldrh w8, [x8]
; CHECK-NEXT:    eor w8, w8, w9
; CHECK-NEXT:    mov w9, #65535
; CHECK-NEXT:    add w8, w8, w9
; CHECK-NEXT:    and w0, w8, w8, lsr #16
; CHECK-NEXT:    ret
entry:
  %0 = load i16, ptr @g, align 4
  %1 = xor i16 %0, 50
  %tobool = icmp ne i16 %1, 0
  %lor.ext = zext i1 %tobool to i32
  %sub = add i16 %1, -1

  %srl = zext i16 %sub to i32
  %and = and i32 %srl, %lor.ext

  ret i32 %and
}