1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 -mattr=+sve -aarch64-sve-vector-bits-min=256 | FileCheck %s
define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) {
; CHECK-LABEL: llrint_v1i64_v1f16:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx h0, h0
; CHECK-NEXT: fcvtzs x8, h0
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret
%a = call <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half> %x)
ret <1 x i64> %a
}
declare <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half>)
define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) {
; CHECK-LABEL: llrint_v1i64_v2f16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov h1, v0.h[1]
; CHECK-NEXT: frintx h0, h0
; CHECK-NEXT: frintx h1, h1
; CHECK-NEXT: fcvtzs x8, h0
; CHECK-NEXT: fcvtzs x9, h1
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: mov v0.d[1], x9
; CHECK-NEXT: ret
%a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x)
ret <2 x i64> %a
}
declare <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half>)
define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) {
; CHECK-LABEL: llrint_v4i64_v4f16:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v0.4h, v0.4h
; CHECK-NEXT: mov h1, v0.h[2]
; CHECK-NEXT: mov h2, v0.h[3]
; CHECK-NEXT: mov h3, v0.h[1]
; CHECK-NEXT: fcvtzs x9, h0
; CHECK-NEXT: fcvtzs x8, h1
; CHECK-NEXT: fcvtzs x10, h2
; CHECK-NEXT: fcvtzs x11, h3
; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: mov v0.d[1], x11
; CHECK-NEXT: mov v1.d[1], x10
; CHECK-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x)
ret <4 x i64> %a
}
declare <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half>)
define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) {
; CHECK-LABEL: llrint_v8i64_v8f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: frintx v0.4h, v0.4h
; CHECK-NEXT: frintx v1.4h, v1.4h
; CHECK-NEXT: mov h4, v0.h[2]
; CHECK-NEXT: mov h2, v0.h[1]
; CHECK-NEXT: mov h7, v0.h[3]
; CHECK-NEXT: fcvtzs x8, h0
; CHECK-NEXT: mov h3, v1.h[2]
; CHECK-NEXT: mov h5, v1.h[3]
; CHECK-NEXT: mov h6, v1.h[1]
; CHECK-NEXT: fcvtzs x11, h1
; CHECK-NEXT: fcvtzs x12, h4
; CHECK-NEXT: fcvtzs x9, h2
; CHECK-NEXT: fcvtzs x15, h7
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: fcvtzs x10, h3
; CHECK-NEXT: fcvtzs x13, h5
; CHECK-NEXT: fcvtzs x14, h6
; CHECK-NEXT: fmov d1, x12
; CHECK-NEXT: fmov d2, x11
; CHECK-NEXT: mov v0.d[1], x9
; CHECK-NEXT: fmov d3, x10
; CHECK-NEXT: mov v1.d[1], x15
; CHECK-NEXT: mov v2.d[1], x14
; CHECK-NEXT: mov v3.d[1], x13
; CHECK-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x)
ret <8 x i64> %a
}
declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)
define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) {
; CHECK-LABEL: llrint_v16i64_v16f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: frintx v1.4h, v1.4h
; CHECK-NEXT: frintx v3.4h, v0.4h
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: frintx v2.4h, v2.4h
; CHECK-NEXT: mov h4, v1.h[2]
; CHECK-NEXT: mov h5, v3.h[2]
; CHECK-NEXT: frintx v0.4h, v0.4h
; CHECK-NEXT: mov h6, v3.h[1]
; CHECK-NEXT: fcvtzs x9, h3
; CHECK-NEXT: mov h16, v1.h[1]
; CHECK-NEXT: fcvtzs x12, h1
; CHECK-NEXT: mov h3, v3.h[3]
; CHECK-NEXT: mov h17, v1.h[3]
; CHECK-NEXT: mov h7, v2.h[3]
; CHECK-NEXT: fcvtzs x8, h4
; CHECK-NEXT: fcvtzs x10, h5
; CHECK-NEXT: mov h4, v2.h[2]
; CHECK-NEXT: mov h5, v0.h[2]
; CHECK-NEXT: fcvtzs x11, h6
; CHECK-NEXT: mov h6, v0.h[3]
; CHECK-NEXT: fcvtzs x15, h2
; CHECK-NEXT: mov h2, v2.h[1]
; CHECK-NEXT: fcvtzs x14, h0
; CHECK-NEXT: fcvtzs x17, h3
; CHECK-NEXT: fcvtzs x0, h17
; CHECK-NEXT: fcvtzs x13, h7
; CHECK-NEXT: mov h7, v0.h[1]
; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: fcvtzs x16, h4
; CHECK-NEXT: fcvtzs x9, h5
; CHECK-NEXT: fmov d4, x12
; CHECK-NEXT: fcvtzs x12, h16
; CHECK-NEXT: fmov d1, x10
; CHECK-NEXT: fcvtzs x10, h6
; CHECK-NEXT: fmov d5, x8
; CHECK-NEXT: fcvtzs x8, h2
; CHECK-NEXT: fmov d2, x14
; CHECK-NEXT: fcvtzs x18, h7
; CHECK-NEXT: fmov d6, x15
; CHECK-NEXT: mov v0.d[1], x11
; CHECK-NEXT: fmov d3, x9
; CHECK-NEXT: fmov d7, x16
; CHECK-NEXT: mov v1.d[1], x17
; CHECK-NEXT: mov v4.d[1], x12
; CHECK-NEXT: mov v5.d[1], x0
; CHECK-NEXT: mov v6.d[1], x8
; CHECK-NEXT: mov v2.d[1], x18
; CHECK-NEXT: mov v3.d[1], x10
; CHECK-NEXT: mov v7.d[1], x13
; CHECK-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)
ret <16 x i64> %a
}
declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>)
define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) {
; CHECK-LABEL: llrint_v32i64_v32f16:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: sub x9, sp, #272
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: frintx v5.4h, v0.4h
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: ext v17.16b, v2.16b, v2.16b, #8
; CHECK-NEXT: frintx v1.4h, v1.4h
; CHECK-NEXT: frintx v2.4h, v2.4h
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: mov h6, v5.h[3]
; CHECK-NEXT: frintx v0.4h, v0.4h
; CHECK-NEXT: mov h7, v5.h[2]
; CHECK-NEXT: mov h16, v5.h[1]
; CHECK-NEXT: frintx v4.4h, v4.4h
; CHECK-NEXT: fcvtzs x12, h5
; CHECK-NEXT: ext v5.16b, v3.16b, v3.16b, #8
; CHECK-NEXT: frintx v17.4h, v17.4h
; CHECK-NEXT: frintx v3.4h, v3.4h
; CHECK-NEXT: fcvtzs x9, h6
; CHECK-NEXT: mov h6, v0.h[3]
; CHECK-NEXT: fcvtzs x10, h7
; CHECK-NEXT: mov h7, v0.h[2]
; CHECK-NEXT: fcvtzs x11, h16
; CHECK-NEXT: mov h16, v0.h[1]
; CHECK-NEXT: fcvtzs x13, h6
; CHECK-NEXT: mov h6, v4.h[3]
; CHECK-NEXT: stp x10, x9, [sp, #48]
; CHECK-NEXT: fcvtzs x9, h7
; CHECK-NEXT: mov h7, v4.h[2]
; CHECK-NEXT: fcvtzs x10, h16
; CHECK-NEXT: mov h16, v4.h[1]
; CHECK-NEXT: stp x12, x11, [sp, #32]
; CHECK-NEXT: fcvtzs x11, h0
; CHECK-NEXT: frintx v0.4h, v5.4h
; CHECK-NEXT: mov h5, v17.h[3]
; CHECK-NEXT: fcvtzs x12, h6
; CHECK-NEXT: mov h6, v17.h[2]
; CHECK-NEXT: stp x9, x13, [sp, #16]
; CHECK-NEXT: fcvtzs x13, h7
; CHECK-NEXT: mov h7, v17.h[1]
; CHECK-NEXT: fcvtzs x9, h16
; CHECK-NEXT: stp x11, x10, [sp]
; CHECK-NEXT: fcvtzs x10, h4
; CHECK-NEXT: fcvtzs x11, h5
; CHECK-NEXT: mov h4, v0.h[3]
; CHECK-NEXT: mov h5, v0.h[2]
; CHECK-NEXT: stp x13, x12, [sp, #80]
; CHECK-NEXT: fcvtzs x12, h6
; CHECK-NEXT: fcvtzs x13, h7
; CHECK-NEXT: mov h6, v0.h[1]
; CHECK-NEXT: stp x10, x9, [sp, #64]
; CHECK-NEXT: fcvtzs x9, h17
; CHECK-NEXT: mov h7, v1.h[3]
; CHECK-NEXT: fcvtzs x10, h4
; CHECK-NEXT: mov h4, v1.h[2]
; CHECK-NEXT: stp x12, x11, [sp, #144]
; CHECK-NEXT: fcvtzs x11, h5
; CHECK-NEXT: mov h5, v1.h[1]
; CHECK-NEXT: fcvtzs x12, h6
; CHECK-NEXT: stp x9, x13, [sp, #128]
; CHECK-NEXT: fcvtzs x9, h0
; CHECK-NEXT: fcvtzs x13, h7
; CHECK-NEXT: mov h0, v2.h[3]
; CHECK-NEXT: stp x11, x10, [sp, #208]
; CHECK-NEXT: fcvtzs x10, h4
; CHECK-NEXT: mov h4, v2.h[2]
; CHECK-NEXT: fcvtzs x11, h5
; CHECK-NEXT: mov h5, v2.h[1]
; CHECK-NEXT: stp x9, x12, [sp, #192]
; CHECK-NEXT: fcvtzs x9, h1
; CHECK-NEXT: fcvtzs x12, h0
; CHECK-NEXT: mov h0, v3.h[3]
; CHECK-NEXT: mov h1, v3.h[2]
; CHECK-NEXT: stp x10, x13, [sp, #112]
; CHECK-NEXT: fcvtzs x10, h4
; CHECK-NEXT: mov h4, v3.h[1]
; CHECK-NEXT: fcvtzs x13, h5
; CHECK-NEXT: stp x9, x11, [sp, #96]
; CHECK-NEXT: fcvtzs x9, h2
; CHECK-NEXT: fcvtzs x11, h0
; CHECK-NEXT: stp x10, x12, [sp, #176]
; CHECK-NEXT: fcvtzs x10, h1
; CHECK-NEXT: fcvtzs x12, h4
; CHECK-NEXT: stp x9, x13, [sp, #160]
; CHECK-NEXT: fcvtzs x9, h3
; CHECK-NEXT: stp x10, x11, [sp, #240]
; CHECK-NEXT: add x10, sp, #64
; CHECK-NEXT: stp x9, x12, [sp, #224]
; CHECK-NEXT: add x9, sp, #32
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9]
; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x10]
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x9]
; CHECK-NEXT: add x9, sp, #224
; CHECK-NEXT: add x10, sp, #128
; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]
; CHECK-NEXT: add x9, sp, #160
; CHECK-NEXT: ld1d { z4.d }, p0/z, [x10]
; CHECK-NEXT: add x10, sp, #96
; CHECK-NEXT: ld1d { z5.d }, p0/z, [x9]
; CHECK-NEXT: add x9, sp, #192
; CHECK-NEXT: ld1d { z6.d }, p0/z, [x10]
; CHECK-NEXT: mov x10, #24 // =0x18
; CHECK-NEXT: ld1d { z7.d }, p0/z, [x9]
; CHECK-NEXT: mov x9, #16 // =0x10
; CHECK-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #8 // =0x8
; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #28 // =0x1c
; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #20 // =0x14
; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #12 // =0xc
; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #4 // =0x4
; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: st1d { z0.d }, p0, [x8]
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%a = call <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half> %x)
ret <32 x i64> %a
}
declare <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half>)
define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) {
; CHECK-LABEL: llrint_v1i64_v1f32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: frintx s0, s0
; CHECK-NEXT: fcvtzs x8, s0
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret
%a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x)
ret <1 x i64> %a
}
declare <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float>)
define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) {
; CHECK-LABEL: llrint_v2i64_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v0.2s, v0.2s
; CHECK-NEXT: fcvtl v0.2d, v0.2s
; CHECK-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-NEXT: ret
%a = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> %x)
ret <2 x i64> %a
}
declare <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float>)
define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) {
; CHECK-LABEL: llrint_v4i64_v4f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v0.4s, v0.4s
; CHECK-NEXT: mov s1, v0.s[2]
; CHECK-NEXT: mov s2, v0.s[3]
; CHECK-NEXT: mov s3, v0.s[1]
; CHECK-NEXT: fcvtzs x9, s0
; CHECK-NEXT: fcvtzs x8, s1
; CHECK-NEXT: fcvtzs x10, s2
; CHECK-NEXT: fcvtzs x11, s3
; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: mov v0.d[1], x11
; CHECK-NEXT: mov v1.d[1], x10
; CHECK-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x)
ret <4 x i64> %a
}
declare <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float>)
define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) {
; CHECK-LABEL: llrint_v8i64_v8f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v0.4s, v0.4s
; CHECK-NEXT: frintx v1.4s, v1.4s
; CHECK-NEXT: mov s3, v1.s[2]
; CHECK-NEXT: mov s4, v0.s[2]
; CHECK-NEXT: mov s2, v0.s[1]
; CHECK-NEXT: mov s5, v1.s[3]
; CHECK-NEXT: mov s6, v1.s[1]
; CHECK-NEXT: mov s7, v0.s[3]
; CHECK-NEXT: fcvtzs x8, s0
; CHECK-NEXT: fcvtzs x10, s1
; CHECK-NEXT: fcvtzs x11, s3
; CHECK-NEXT: fcvtzs x12, s4
; CHECK-NEXT: fcvtzs x9, s2
; CHECK-NEXT: fcvtzs x13, s5
; CHECK-NEXT: fcvtzs x14, s6
; CHECK-NEXT: fcvtzs x15, s7
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: fmov d2, x10
; CHECK-NEXT: fmov d1, x12
; CHECK-NEXT: fmov d3, x11
; CHECK-NEXT: mov v0.d[1], x9
; CHECK-NEXT: mov v2.d[1], x14
; CHECK-NEXT: mov v1.d[1], x15
; CHECK-NEXT: mov v3.d[1], x13
; CHECK-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x)
ret <8 x i64> %a
}
declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)
define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) {
; CHECK-LABEL: llrint_v16i64_v16f32:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v3.4s, v3.4s
; CHECK-NEXT: frintx v2.4s, v2.4s
; CHECK-NEXT: frintx v1.4s, v1.4s
; CHECK-NEXT: frintx v0.4s, v0.4s
; CHECK-NEXT: mov s4, v3.s[2]
; CHECK-NEXT: mov s5, v2.s[2]
; CHECK-NEXT: mov s6, v1.s[2]
; CHECK-NEXT: mov s7, v0.s[2]
; CHECK-NEXT: fcvtzs x10, s1
; CHECK-NEXT: fcvtzs x11, s0
; CHECK-NEXT: mov s16, v0.s[1]
; CHECK-NEXT: mov s17, v1.s[1]
; CHECK-NEXT: mov s18, v3.s[1]
; CHECK-NEXT: fcvtzs x14, s3
; CHECK-NEXT: fcvtzs x16, s2
; CHECK-NEXT: fcvtzs x8, s4
; CHECK-NEXT: mov s4, v2.s[1]
; CHECK-NEXT: fcvtzs x9, s5
; CHECK-NEXT: mov s5, v1.s[3]
; CHECK-NEXT: fcvtzs x12, s6
; CHECK-NEXT: mov s6, v0.s[3]
; CHECK-NEXT: fcvtzs x13, s7
; CHECK-NEXT: mov s7, v3.s[3]
; CHECK-NEXT: fmov d0, x11
; CHECK-NEXT: fcvtzs x17, s16
; CHECK-NEXT: fcvtzs x18, s18
; CHECK-NEXT: fcvtzs x15, s4
; CHECK-NEXT: mov s4, v2.s[3]
; CHECK-NEXT: fmov d2, x10
; CHECK-NEXT: fcvtzs x11, s5
; CHECK-NEXT: fcvtzs x10, s6
; CHECK-NEXT: fmov d3, x12
; CHECK-NEXT: fmov d1, x13
; CHECK-NEXT: fcvtzs x12, s17
; CHECK-NEXT: fcvtzs x13, s7
; CHECK-NEXT: fmov d5, x9
; CHECK-NEXT: fmov d6, x14
; CHECK-NEXT: fmov d7, x8
; CHECK-NEXT: fcvtzs x0, s4
; CHECK-NEXT: fmov d4, x16
; CHECK-NEXT: mov v0.d[1], x17
; CHECK-NEXT: mov v1.d[1], x10
; CHECK-NEXT: mov v3.d[1], x11
; CHECK-NEXT: mov v2.d[1], x12
; CHECK-NEXT: mov v6.d[1], x18
; CHECK-NEXT: mov v7.d[1], x13
; CHECK-NEXT: mov v4.d[1], x15
; CHECK-NEXT: mov v5.d[1], x0
; CHECK-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x)
ret <16 x i64> %a
}
declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)
define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) {
; CHECK-LABEL: llrint_v32i64_v32f32:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: sub x9, sp, #272
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: frintx v0.4s, v0.4s
; CHECK-NEXT: frintx v1.4s, v1.4s
; CHECK-NEXT: frintx v2.4s, v2.4s
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: mov s16, v0.s[3]
; CHECK-NEXT: mov s17, v0.s[2]
; CHECK-NEXT: mov s18, v0.s[1]
; CHECK-NEXT: fcvtzs x12, s0
; CHECK-NEXT: frintx v0.4s, v3.4s
; CHECK-NEXT: mov s3, v2.s[3]
; CHECK-NEXT: fcvtzs x9, s16
; CHECK-NEXT: mov s16, v1.s[3]
; CHECK-NEXT: fcvtzs x10, s17
; CHECK-NEXT: mov s17, v1.s[2]
; CHECK-NEXT: fcvtzs x11, s18
; CHECK-NEXT: mov s18, v1.s[1]
; CHECK-NEXT: fcvtzs x13, s16
; CHECK-NEXT: stp x10, x9, [sp, #16]
; CHECK-NEXT: mov s16, v2.s[2]
; CHECK-NEXT: fcvtzs x9, s17
; CHECK-NEXT: fcvtzs x10, s18
; CHECK-NEXT: mov s17, v2.s[1]
; CHECK-NEXT: stp x12, x11, [sp]
; CHECK-NEXT: fcvtzs x11, s1
; CHECK-NEXT: frintx v1.4s, v4.4s
; CHECK-NEXT: fcvtzs x12, s3
; CHECK-NEXT: mov s3, v0.s[3]
; CHECK-NEXT: mov s4, v0.s[2]
; CHECK-NEXT: stp x9, x13, [sp, #48]
; CHECK-NEXT: fcvtzs x13, s16
; CHECK-NEXT: fcvtzs x9, s17
; CHECK-NEXT: mov s16, v0.s[1]
; CHECK-NEXT: stp x11, x10, [sp, #32]
; CHECK-NEXT: fcvtzs x10, s2
; CHECK-NEXT: frintx v2.4s, v5.4s
; CHECK-NEXT: fcvtzs x11, s3
; CHECK-NEXT: mov s3, v1.s[3]
; CHECK-NEXT: mov s5, v1.s[1]
; CHECK-NEXT: stp x13, x12, [sp, #80]
; CHECK-NEXT: fcvtzs x12, s4
; CHECK-NEXT: mov s4, v1.s[2]
; CHECK-NEXT: fcvtzs x13, s16
; CHECK-NEXT: stp x10, x9, [sp, #64]
; CHECK-NEXT: fcvtzs x9, s0
; CHECK-NEXT: mov s0, v2.s[3]
; CHECK-NEXT: fcvtzs x10, s3
; CHECK-NEXT: frintx v3.4s, v6.4s
; CHECK-NEXT: stp x12, x11, [sp, #112]
; CHECK-NEXT: fcvtzs x11, s4
; CHECK-NEXT: mov s4, v2.s[2]
; CHECK-NEXT: fcvtzs x12, s5
; CHECK-NEXT: mov s5, v2.s[1]
; CHECK-NEXT: stp x9, x13, [sp, #96]
; CHECK-NEXT: fcvtzs x9, s1
; CHECK-NEXT: fcvtzs x13, s0
; CHECK-NEXT: mov s0, v3.s[3]
; CHECK-NEXT: frintx v1.4s, v7.4s
; CHECK-NEXT: stp x11, x10, [sp, #144]
; CHECK-NEXT: fcvtzs x10, s4
; CHECK-NEXT: mov s4, v3.s[2]
; CHECK-NEXT: fcvtzs x11, s5
; CHECK-NEXT: mov s5, v3.s[1]
; CHECK-NEXT: stp x9, x12, [sp, #128]
; CHECK-NEXT: fcvtzs x9, s2
; CHECK-NEXT: fcvtzs x12, s0
; CHECK-NEXT: mov s0, v1.s[3]
; CHECK-NEXT: mov s2, v1.s[2]
; CHECK-NEXT: stp x10, x13, [sp, #176]
; CHECK-NEXT: fcvtzs x10, s4
; CHECK-NEXT: mov s4, v1.s[1]
; CHECK-NEXT: fcvtzs x13, s5
; CHECK-NEXT: stp x9, x11, [sp, #160]
; CHECK-NEXT: fcvtzs x9, s3
; CHECK-NEXT: fcvtzs x11, s0
; CHECK-NEXT: stp x10, x12, [sp, #208]
; CHECK-NEXT: fcvtzs x10, s2
; CHECK-NEXT: fcvtzs x12, s4
; CHECK-NEXT: stp x9, x13, [sp, #192]
; CHECK-NEXT: fcvtzs x9, s1
; CHECK-NEXT: stp x10, x11, [sp, #240]
; CHECK-NEXT: add x10, sp, #64
; CHECK-NEXT: stp x9, x12, [sp, #224]
; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9]
; CHECK-NEXT: add x9, sp, #32
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x10]
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x9]
; CHECK-NEXT: add x9, sp, #224
; CHECK-NEXT: add x10, sp, #96
; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]
; CHECK-NEXT: add x9, sp, #192
; CHECK-NEXT: ld1d { z4.d }, p0/z, [x10]
; CHECK-NEXT: add x10, sp, #160
; CHECK-NEXT: ld1d { z5.d }, p0/z, [x9]
; CHECK-NEXT: add x9, sp, #128
; CHECK-NEXT: ld1d { z6.d }, p0/z, [x10]
; CHECK-NEXT: mov x10, #28 // =0x1c
; CHECK-NEXT: ld1d { z7.d }, p0/z, [x9]
; CHECK-NEXT: mov x9, #24 // =0x18
; CHECK-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #20 // =0x14
; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #16 // =0x10
; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #12 // =0xc
; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #8 // =0x8
; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #4 // =0x4
; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: st1d { z0.d }, p0, [x8]
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%a = call <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float> %x)
ret <32 x i64> %a
}
declare <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float>)
define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) {
; CHECK-LABEL: llrint_v1i64_v1f64:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx d0, d0
; CHECK-NEXT: fcvtzs x8, d0
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret
%a = call <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double> %x)
ret <1 x i64> %a
}
declare <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double>)
define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) {
; CHECK-LABEL: llrint_v2i64_v2f64:
; CHECK: // %bb.0:
; CHECK-NEXT: frintx v0.2d, v0.2d
; CHECK-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-NEXT: ret
%a = call <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double> %x)
ret <2 x i64> %a
}
declare <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double>)
define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) {
; CHECK-LABEL: llrint_v4i64_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: mov z1.d, z0.d[2]
; CHECK-NEXT: mov z2.d, z0.d[3]
; CHECK-NEXT: mov z3.d, z0.d[1]
; CHECK-NEXT: fcvtzs x9, d0
; CHECK-NEXT: fcvtzs x8, d1
; CHECK-NEXT: fcvtzs x10, d2
; CHECK-NEXT: fcvtzs x11, d3
; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: mov v0.d[1], x11
; CHECK-NEXT: mov v1.d[1], x10
; CHECK-NEXT: ret
%a = call <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double> %x)
ret <4 x i64> %a
}
declare <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double>)
define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) {
; CHECK-LABEL: llrint_v8i64_v8f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d
; CHECK-NEXT: splice z2.d, p0, z2.d, z3.d
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: movprfx z1, z2
; CHECK-NEXT: frintx z1.d, p0/m, z2.d
; CHECK-NEXT: mov z4.d, z1.d[2]
; CHECK-NEXT: mov z5.d, z0.d[2]
; CHECK-NEXT: mov z2.d, z0.d[1]
; CHECK-NEXT: mov z3.d, z1.d[3]
; CHECK-NEXT: mov z6.d, z0.d[3]
; CHECK-NEXT: fcvtzs x8, d0
; CHECK-NEXT: mov z0.d, z1.d[1]
; CHECK-NEXT: fcvtzs x10, d1
; CHECK-NEXT: fcvtzs x11, d4
; CHECK-NEXT: fcvtzs x12, d5
; CHECK-NEXT: fcvtzs x9, d2
; CHECK-NEXT: fcvtzs x13, d3
; CHECK-NEXT: fcvtzs x14, d6
; CHECK-NEXT: fcvtzs x15, d0
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: fmov d2, x10
; CHECK-NEXT: fmov d1, x12
; CHECK-NEXT: fmov d3, x11
; CHECK-NEXT: mov v0.d[1], x9
; CHECK-NEXT: mov v2.d[1], x15
; CHECK-NEXT: mov v1.d[1], x14
; CHECK-NEXT: mov v3.d[1], x13
; CHECK-NEXT: ret
%a = call <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double> %x)
ret <8 x i64> %a
}
declare <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double>)
define <16 x i64> @llrint_v16f64(<16 x double> %x) {
; CHECK-LABEL: llrint_v16f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p1.d, vl2
; CHECK-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-NEXT: // kill: def $q7 killed $q7 def $z7
; CHECK-NEXT: // kill: def $q5 killed $q5 def $z5
; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: splice z6.d, p1, z6.d, z7.d
; CHECK-NEXT: splice z4.d, p1, z4.d, z5.d
; CHECK-NEXT: splice z2.d, p1, z2.d, z3.d
; CHECK-NEXT: splice z0.d, p1, z0.d, z1.d
; CHECK-NEXT: movprfx z3, z6
; CHECK-NEXT: frintx z3.d, p0/m, z6.d
; CHECK-NEXT: movprfx z1, z4
; CHECK-NEXT: frintx z1.d, p0/m, z4.d
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: mov z4.d, z3.d[2]
; CHECK-NEXT: mov z5.d, z1.d[2]
; CHECK-NEXT: mov z6.d, z2.d[3]
; CHECK-NEXT: fcvtzs x11, d0
; CHECK-NEXT: fcvtzs x12, d1
; CHECK-NEXT: fcvtzs x13, d2
; CHECK-NEXT: fcvtzs x14, d3
; CHECK-NEXT: mov z7.d, z3.d[3]
; CHECK-NEXT: mov z16.d, z1.d[3]
; CHECK-NEXT: fcvtzs x9, d4
; CHECK-NEXT: fcvtzs x10, d5
; CHECK-NEXT: mov z4.d, z2.d[2]
; CHECK-NEXT: mov z5.d, z0.d[2]
; CHECK-NEXT: fcvtzs x8, d6
; CHECK-NEXT: mov z2.d, z2.d[1]
; CHECK-NEXT: mov z6.d, z0.d[3]
; CHECK-NEXT: mov z1.d, z1.d[1]
; CHECK-NEXT: mov z3.d, z3.d[1]
; CHECK-NEXT: fcvtzs x15, d4
; CHECK-NEXT: mov z4.d, z0.d[1]
; CHECK-NEXT: fmov d0, x11
; CHECK-NEXT: fcvtzs x16, d5
; CHECK-NEXT: fcvtzs x11, d2
; CHECK-NEXT: fmov d2, x13
; CHECK-NEXT: fcvtzs x17, d7
; CHECK-NEXT: fcvtzs x18, d16
; CHECK-NEXT: fcvtzs x0, d3
; CHECK-NEXT: fcvtzs x13, d4
; CHECK-NEXT: fmov d4, x12
; CHECK-NEXT: fcvtzs x12, d6
; CHECK-NEXT: fmov d6, x14
; CHECK-NEXT: fcvtzs x14, d1
; CHECK-NEXT: fmov d3, x15
; CHECK-NEXT: fmov d1, x16
; CHECK-NEXT: fmov d5, x10
; CHECK-NEXT: fmov d7, x9
; CHECK-NEXT: mov v2.d[1], x11
; CHECK-NEXT: mov v0.d[1], x13
; CHECK-NEXT: mov v3.d[1], x8
; CHECK-NEXT: mov v6.d[1], x0
; CHECK-NEXT: mov v4.d[1], x14
; CHECK-NEXT: mov v1.d[1], x12
; CHECK-NEXT: mov v5.d[1], x18
; CHECK-NEXT: mov v7.d[1], x17
; CHECK-NEXT: ret
%a = call <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double> %x)
ret <16 x i64> %a
}
declare <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double>)
define <32 x i64> @llrint_v32f64(<32 x double> %x) {
; CHECK-LABEL: llrint_v32f64:
; CHECK: // %bb.0:
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: sub x9, sp, #272
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0
; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: ptrue p1.d, vl2
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT: // kill: def $q7 killed $q7 def $z7
; CHECK-NEXT: // kill: def $q6 killed $q6 def $z6
; CHECK-NEXT: // kill: def $q4 killed $q4 def $z4
; CHECK-NEXT: // kill: def $q5 killed $q5 def $z5
; CHECK-NEXT: ptrue p0.d, vl4
; CHECK-NEXT: splice z0.d, p1, z0.d, z1.d
; CHECK-NEXT: splice z2.d, p1, z2.d, z3.d
; CHECK-NEXT: splice z4.d, p1, z4.d, z5.d
; CHECK-NEXT: splice z6.d, p1, z6.d, z7.d
; CHECK-NEXT: ldp q5, q19, [x29, #16]
; CHECK-NEXT: movprfx z3, z0
; CHECK-NEXT: frintx z3.d, p0/m, z0.d
; CHECK-NEXT: movprfx z16, z2
; CHECK-NEXT: frintx z16.d, p0/m, z2.d
; CHECK-NEXT: frintx z4.d, p0/m, z4.d
; CHECK-NEXT: splice z5.d, p1, z5.d, z19.d
; CHECK-NEXT: frintx z6.d, p0/m, z6.d
; CHECK-NEXT: ldp q2, q17, [x29, #48]
; CHECK-NEXT: ldp q0, q1, [x29, #112]
; CHECK-NEXT: mov z18.d, z3.d[3]
; CHECK-NEXT: mov z7.d, z3.d[2]
; CHECK-NEXT: fcvtzs x9, d3
; CHECK-NEXT: mov z3.d, z3.d[1]
; CHECK-NEXT: mov z20.d, z16.d[3]
; CHECK-NEXT: fcvtzs x12, d16
; CHECK-NEXT: splice z2.d, p1, z2.d, z17.d
; CHECK-NEXT: frintx z5.d, p0/m, z5.d
; CHECK-NEXT: splice z0.d, p1, z0.d, z1.d
; CHECK-NEXT: fcvtzs x10, d18
; CHECK-NEXT: fcvtzs x11, d7
; CHECK-NEXT: mov z18.d, z16.d[2]
; CHECK-NEXT: mov z7.d, z16.d[1]
; CHECK-NEXT: fcvtzs x13, d3
; CHECK-NEXT: fcvtzs x14, d20
; CHECK-NEXT: str x9, [sp, #128]
; CHECK-NEXT: mov z16.d, z4.d[3]
; CHECK-NEXT: fcvtzs x9, d18
; CHECK-NEXT: mov z18.d, z4.d[2]
; CHECK-NEXT: frintx z2.d, p0/m, z2.d
; CHECK-NEXT: stp x11, x10, [sp, #144]
; CHECK-NEXT: fcvtzs x10, d7
; CHECK-NEXT: mov z7.d, z4.d[1]
; CHECK-NEXT: str x13, [sp, #136]
; CHECK-NEXT: fcvtzs x11, d16
; CHECK-NEXT: mov z16.d, z6.d[3]
; CHECK-NEXT: fcvtzs x13, d18
; CHECK-NEXT: ldp q3, q19, [x29, #80]
; CHECK-NEXT: stp x9, x14, [sp, #176]
; CHECK-NEXT: fcvtzs x9, d4
; CHECK-NEXT: mov z4.d, z6.d[2]
; CHECK-NEXT: stp x12, x10, [sp, #160]
; CHECK-NEXT: fcvtzs x10, d7
; CHECK-NEXT: mov z7.d, z6.d[1]
; CHECK-NEXT: fcvtzs x12, d6
; CHECK-NEXT: splice z3.d, p1, z3.d, z19.d
; CHECK-NEXT: mov z6.d, z5.d[2]
; CHECK-NEXT: stp x13, x11, [sp, #208]
; CHECK-NEXT: fcvtzs x11, d16
; CHECK-NEXT: fcvtzs x13, d4
; CHECK-NEXT: mov z4.d, z5.d[3]
; CHECK-NEXT: mov z1.d, z5.d[1]
; CHECK-NEXT: frintx z0.d, p0/m, z0.d
; CHECK-NEXT: stp x9, x10, [sp, #192]
; CHECK-NEXT: fcvtzs x9, d7
; CHECK-NEXT: frintx z3.d, p0/m, z3.d
; CHECK-NEXT: fcvtzs x10, d4
; CHECK-NEXT: stp x13, x11, [sp, #240]
; CHECK-NEXT: fcvtzs x11, d6
; CHECK-NEXT: mov z4.d, z2.d[3]
; CHECK-NEXT: fcvtzs x13, d2
; CHECK-NEXT: stp x12, x9, [sp, #224]
; CHECK-NEXT: fcvtzs x9, d5
; CHECK-NEXT: fcvtzs x12, d1
; CHECK-NEXT: mov z5.d, z2.d[2]
; CHECK-NEXT: mov z1.d, z2.d[1]
; CHECK-NEXT: mov z2.d, z3.d[2]
; CHECK-NEXT: stp x11, x10, [sp, #16]
; CHECK-NEXT: fcvtzs x10, d4
; CHECK-NEXT: mov z4.d, z3.d[3]
; CHECK-NEXT: fcvtzs x11, d5
; CHECK-NEXT: stp x9, x12, [sp]
; CHECK-NEXT: fcvtzs x9, d1
; CHECK-NEXT: mov z1.d, z3.d[1]
; CHECK-NEXT: fcvtzs x12, d4
; CHECK-NEXT: stp x11, x10, [sp, #48]
; CHECK-NEXT: fcvtzs x10, d2
; CHECK-NEXT: fcvtzs x11, d3
; CHECK-NEXT: stp x13, x9, [sp, #32]
; CHECK-NEXT: fcvtzs x9, d1
; CHECK-NEXT: mov z2.d, z0.d[3]
; CHECK-NEXT: mov z3.d, z0.d[2]
; CHECK-NEXT: mov z1.d, z0.d[1]
; CHECK-NEXT: fcvtzs x13, d2
; CHECK-NEXT: stp x10, x12, [sp, #80]
; CHECK-NEXT: fcvtzs x12, d0
; CHECK-NEXT: fcvtzs x10, d3
; CHECK-NEXT: stp x11, x9, [sp, #64]
; CHECK-NEXT: fcvtzs x9, d1
; CHECK-NEXT: stp x10, x13, [sp, #112]
; CHECK-NEXT: add x10, sp, #192
; CHECK-NEXT: stp x12, x9, [sp, #96]
; CHECK-NEXT: add x9, sp, #128
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x9]
; CHECK-NEXT: add x9, sp, #160
; CHECK-NEXT: ld1d { z2.d }, p0/z, [x10]
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x9]
; CHECK-NEXT: add x9, sp, #96
; CHECK-NEXT: add x10, sp, #224
; CHECK-NEXT: ld1d { z3.d }, p0/z, [x9]
; CHECK-NEXT: add x9, sp, #64
; CHECK-NEXT: ld1d { z4.d }, p0/z, [x10]
; CHECK-NEXT: add x10, sp, #32
; CHECK-NEXT: ld1d { z5.d }, p0/z, [x9]
; CHECK-NEXT: mov x9, sp
; CHECK-NEXT: ld1d { z6.d }, p0/z, [x10]
; CHECK-NEXT: mov x10, #28 // =0x1c
; CHECK-NEXT: ld1d { z7.d }, p0/z, [x9]
; CHECK-NEXT: mov x9, #24 // =0x18
; CHECK-NEXT: st1d { z3.d }, p0, [x8, x10, lsl #3]
; CHECK-NEXT: st1d { z5.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #20 // =0x14
; CHECK-NEXT: st1d { z6.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #16 // =0x10
; CHECK-NEXT: st1d { z7.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #12 // =0xc
; CHECK-NEXT: st1d { z4.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #8 // =0x8
; CHECK-NEXT: st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: mov x9, #4 // =0x4
; CHECK-NEXT: st1d { z1.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT: st1d { z0.d }, p0, [x8]
; CHECK-NEXT: mov sp, x29
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
%a = call <32 x i64> @llvm.llrint.v32i64.v16f64(<32 x double> %x)
ret <32 x i64> %a
}
declare <32 x i64> @llvm.llrint.v32i64.v32f64(<32 x double>)
|
