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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s
; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
target triple = "aarch64-unknown-linux-gnu"
define void @hang_when_merging_stores_after_legalisation(ptr %a, <2 x i32> %b) {
; CHECK-LABEL: hang_when_merging_stores_after_legalisation:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: mov z0.s, s0
; CHECK-NEXT: mov z1.d, z0.d
; CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: hang_when_merging_stores_after_legalisation:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #32
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32
; NONEON-NOSVE-NEXT: str d0, [sp, #8]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #8]
; NONEON-NOSVE-NEXT: stp w8, w8, [sp, #24]
; NONEON-NOSVE-NEXT: stp w8, w8, [sp, #16]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
; NONEON-NOSVE-NEXT: stp q0, q0, [x0]
; NONEON-NOSVE-NEXT: add sp, sp, #32
; NONEON-NOSVE-NEXT: ret
%splat = shufflevector <2 x i32> %b, <2 x i32> undef, <8 x i32> zeroinitializer
%interleaved.vec = shufflevector <8 x i32> %splat, <8 x i32> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
store <8 x i32> %interleaved.vec, ptr %a, align 4
ret void
}
define void @interleave_store_without_splat(ptr %a, <4 x i32> %v1, <4 x i32> %v2) {
; CHECK-LABEL: interleave_store_without_splat:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z0_z1 def $z0_z1
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0_z1 def $z0_z1
; CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: interleave_store_without_splat:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #64
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #16]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #36]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #20]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #8]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #32]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #16]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #44]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #28]
; NONEON-NOSVE-NEXT: ldr q1, [sp]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #56]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #40]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #24]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #48]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #48]
; NONEON-NOSVE-NEXT: stp q1, q0, [x0]
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%shuffle = shufflevector <4 x i32> %v1, <4 x i32> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%interleaved = shufflevector <8 x i32> %shuffle, <8 x i32> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
store <8 x i32> %interleaved, ptr %a, align 1
ret void
}
define void @interleave_store_legalization(ptr %a, <8 x i32> %v1, <8 x i32> %v2) {
; CHECK-LABEL: interleave_store_legalization:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z5.d, z2.d
; CHECK-NEXT: // kill: def $q3 killed $q3 def $z2_z3
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: mov x8, #8 // =0x8
; CHECK-NEXT: mov z4.d, z0.d
; CHECK-NEXT: mov z2.d, z1.d
; CHECK-NEXT: st2w { z4.s, z5.s }, p0, [x0]
; CHECK-NEXT: st2w { z2.s, z3.s }, p0, [x0, x8, lsl #2]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: interleave_store_legalization:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #128
; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128
; NONEON-NOSVE-NEXT: stp q1, q3, [sp, #16]
; NONEON-NOSVE-NEXT: stp q0, q2, [sp, #80]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #100]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #84]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #72]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #96]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #80]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #64]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #108]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #92]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #120]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #104]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #88]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #112]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #36]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #20]
; NONEON-NOSVE-NEXT: ldr q3, [sp, #112]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #8]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #32]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #16]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #44]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #28]
; NONEON-NOSVE-NEXT: ldr q1, [sp]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #56]
; NONEON-NOSVE-NEXT: ldr w9, [sp, #40]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #24]
; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #48]
; NONEON-NOSVE-NEXT: ldp q0, q2, [sp, #48]
; NONEON-NOSVE-NEXT: stp q2, q3, [x0]
; NONEON-NOSVE-NEXT: stp q1, q0, [x0, #32]
; NONEON-NOSVE-NEXT: add sp, sp, #128
; NONEON-NOSVE-NEXT: ret
%interleaved.vec = shufflevector <8 x i32> %v1, <8 x i32> %v2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11,
i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
store <16 x i32> %interleaved.vec, ptr %a, align 4
ret void
}
; Ensure we don't crash when trying to lower a shuffle via an extract
define void @crash_when_lowering_extract_shuffle(ptr %dst, i1 %cond) {
; CHECK-LABEL: crash_when_lowering_extract_shuffle:
; CHECK: // %bb.0:
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: crash_when_lowering_extract_shuffle:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ret
%broadcast.splat = shufflevector <32 x i1> zeroinitializer, <32 x i1> zeroinitializer, <32 x i32> zeroinitializer
br i1 %cond, label %exit, label %vector.body
vector.body:
%1 = load <32 x i32>, ptr %dst, align 16
%predphi = select <32 x i1> %broadcast.splat, <32 x i32> zeroinitializer, <32 x i32> %1
store <32 x i32> %predphi, ptr %dst, align 16
br label %exit
exit:
ret void
}
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