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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming < %s | FileCheck %s
define <vscale x 4 x i32> @sdot_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
; CHECK-LABEL: sdot_x2:
; CHECK: // %bb.0:
; CHECK-NEXT: sdot z0.s, z1.h, z2.h
; CHECK-NEXT: ret
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
ret <vscale x 4 x i32> %out
}
define <vscale x 4 x i32> @udot_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
; CHECK-LABEL: udot_x2:
; CHECK: // %bb.0:
; CHECK-NEXT: udot z0.s, z1.h, z2.h
; CHECK-NEXT: ret
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
ret <vscale x 4 x i32> %out
}
define <vscale x 4 x float> @fdot_x2(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm) {
; CHECK-LABEL: fdot_x2:
; CHECK: // %bb.0:
; CHECK-NEXT: fdot z0.s, z1.h, z2.h
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)
ret <vscale x 4 x float> %out
}
define <vscale x 4 x i32> @sdot_lane_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
; CHECK-LABEL: sdot_lane_x2:
; CHECK: // %bb.0:
; CHECK-NEXT: sdot z0.s, z1.h, z2.h[3]
; CHECK-NEXT: ret
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32 3)
ret <vscale x 4 x i32> %out
}
define <vscale x 4 x i32> @udot_lane_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
; CHECK-LABEL: udot_lane_x2:
; CHECK: // %bb.0:
; CHECK-NEXT: udot z0.s, z1.h, z2.h[3]
; CHECK-NEXT: ret
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32 3)
ret <vscale x 4 x i32> %out
}
define <vscale x 4 x float> @fdot_lane_x2(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm) {
; CHECK-LABEL: fdot_lane_x2:
; CHECK: // %bb.0:
; CHECK-NEXT: fdot z0.s, z1.h, z2.h[3]
; CHECK-NEXT: ret
%out = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm, i32 3)
ret <vscale x 4 x float> %out
}
declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)
declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32)
declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32)
declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm, i32)
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