1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
---
name: fconstant_v_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: fconstant_v_s32
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
; GCN-NEXT: $vgpr0 = COPY [[V_MOV_B32_e32_]]
; GCN-NEXT: $vgpr1 = COPY [[V_MOV_B32_e32_1]]
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]]
%0:vgpr(s32) = G_FCONSTANT float 1.0
%1:vgpr(s32) = G_FCONSTANT float 8.0
%2:vgpr(s32) = G_FCONSTANT float 1.0
%3:vgpr(s32) = G_FCONSTANT float 8.0
$vgpr0 = COPY %0
$vgpr1 = COPY %1
S_ENDPGM 0, implicit %2 , implicit %3
...
---
name: fconstant_s_s32
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: fconstant_s_s32
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1065353216
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1090519040
; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 3212836864
; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 3238002688
; GCN-NEXT: $sgpr0 = COPY [[S_MOV_B32_]]
; GCN-NEXT: $sgpr1 = COPY [[S_MOV_B32_1]]
; GCN-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]]
%0:sgpr(s32) = G_FCONSTANT float 1.0
%1:sgpr(s32) = G_FCONSTANT float 8.0
%2:sgpr(s32) = G_FCONSTANT float -1.0
%3:sgpr(s32) = G_FCONSTANT float -8.0
$sgpr0 = COPY %0
$sgpr1 = COPY %1
S_ENDPGM 0, implicit %2 , implicit %3
...
---
name: fconstant_v_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: fconstant_v_s64
; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 4607182418800017408, implicit $exec
; GCN-NEXT: [[V_MOV_B1:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 4620693217682128896, implicit $exec
; GCN-NEXT: [[V_MOV_B2:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO -4611686018427387904, implicit $exec
; GCN-NEXT: [[V_MOV_B3:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 4621819117588971520, implicit $exec
; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_MOV_B]]
; GCN-NEXT: $vgpr2_vgpr3 = COPY [[V_MOV_B1]]
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MOV_B2]], implicit [[V_MOV_B3]]
%0:vgpr(s64) = G_FCONSTANT double 1.0
%1:vgpr(s64) = G_FCONSTANT double 8.0
%2:vgpr(s64) = G_FCONSTANT double -2.0
%3:vgpr(s64) = G_FCONSTANT double 10.0
$vgpr0_vgpr1 = COPY %0
$vgpr2_vgpr3 = COPY %1
S_ENDPGM 0, implicit %2 , implicit %3
...
---
name: fconstant_s_s64
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: fconstant_s_s64
; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4607182418800017408
; GCN-NEXT: [[S_MOV_B1:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 4620693217682128896
; GCN-NEXT: [[S_MOV_B2:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -4611686018427387904
; GCN-NEXT: [[S_MOV_B3:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -4601552919265804288
; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_MOV_B]]
; GCN-NEXT: $sgpr2_sgpr3 = COPY [[S_MOV_B1]]
; GCN-NEXT: S_ENDPGM 0, implicit [[S_MOV_B]], implicit [[S_MOV_B1]], implicit [[S_MOV_B2]], implicit [[S_MOV_B3]]
%0:sgpr(s64) = G_FCONSTANT double 1.0
%1:sgpr(s64) = G_FCONSTANT double 8.0
%2:sgpr(s64) = G_FCONSTANT double -2.0
%3:sgpr(s64) = G_FCONSTANT double -10.0
$sgpr0_sgpr1 = COPY %0
$sgpr2_sgpr3 = COPY %1
S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2 , implicit %3
...
---
name: fconstant_v_s16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: fconstant_v_s16
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 15360, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 18432, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 15360, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 18432, implicit $exec
; GCN-NEXT: $vgpr0 = COPY [[V_MOV_B32_e32_]]
; GCN-NEXT: $vgpr1 = COPY [[V_MOV_B32_e32_1]]
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]]
%0:vgpr(s16) = G_FCONSTANT half 1.0
%1:vgpr(s16) = G_FCONSTANT half 8.0
%2:vgpr(s32) = G_ANYEXT %0
%3:vgpr(s32) = G_ANYEXT %1
%4:vgpr(s16) = G_FCONSTANT half 1.0
%5:vgpr(s16) = G_FCONSTANT half 8.0
$vgpr0 = COPY %2
$vgpr1 = COPY %3
S_ENDPGM 0, implicit %4, implicit %5
...
---
name: fconstant_s_s16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: fconstant_s_s16
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15360
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 18432
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 15360
; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 18432
; GCN-NEXT: $sgpr0 = COPY [[COPY]]
; GCN-NEXT: $sgpr1 = COPY [[COPY1]]
; GCN-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]]
%0:sgpr(s16) = G_FCONSTANT half 1.0
%1:sgpr(s16) = G_FCONSTANT half 8.0
%2:vgpr(s32) = G_ANYEXT %0
%3:vgpr(s32) = G_ANYEXT %1
%4:sgpr(s16) = G_FCONSTANT half 1.0
%5:sgpr(s16) = G_FCONSTANT half 8.0
$sgpr0 = COPY %2
$sgpr1 = COPY %3
S_ENDPGM 0, implicit %4, implicit %5
...
|
