1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass=si-fold-operands -o - %s | FileCheck --check-prefix=GCN %s
---
name: no_fold_fp_64bit_literal_sgpr
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: no_fold_fp_64bit_literal_sgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 1311768467750121200
; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, [[S_MOV_B]], 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_F64_e64_]]
%0:vreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64_IMM_PSEUDO 1311768467750121200
%2:vreg_64 = V_ADD_F64_e64 0, %1, 0, %0, 0, 0, implicit $mode, implicit $exec
SI_RETURN_TO_EPILOG %2
...
---
name: no_fold_fp_64bit_literal_vgpr
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: no_fold_fp_64bit_literal_vgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec
; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, [[V_MOV_B]], 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_F64_e64_]]
%0:vreg_64 = IMPLICIT_DEF
%1:vreg_64 = V_MOV_B64_PSEUDO 1311768467750121200, implicit $exec
%2:vreg_64 = V_ADD_F64_e64 0, %1, 0, %0, 0, 0, implicit $mode, implicit $exec
SI_RETURN_TO_EPILOG %2
...
---
name: fold_fp_32bit_literal_sgpr
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: fold_fp_32bit_literal_sgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[V_ADD_F64_e64_:%[0-9]+]]:vreg_64 = V_ADD_F64_e64 0, 4636737291354636288, 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_ADD_F64_e64_]]
%0:vreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64_IMM_PSEUDO 4636737291354636288
%2:vreg_64 = V_ADD_F64_e64 0, %1, 0, %0, 0, 0, implicit $mode, implicit $exec
SI_RETURN_TO_EPILOG %2
...
---
name: no_fold_int_64bit_literal_sgpr
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: no_fold_int_64bit_literal_sgpr
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 1311768467750121200
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[DEF]], [[S_MOV_B]], implicit-def $scc
; GCN-NEXT: SI_RETURN_TO_EPILOG [[S_AND_B64_]]
%0:sreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64_IMM_PSEUDO 1311768467750121200
%2:sreg_64 = S_AND_B64 %0, %1, implicit-def $scc
SI_RETURN_TO_EPILOG %2
...
---
name: fold_int_32bit_literal_sgpr
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: fold_int_32bit_literal_sgpr
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[DEF]], 2147483647, implicit-def $scc
; GCN-NEXT: SI_RETURN_TO_EPILOG [[S_AND_B64_]]
%0:sreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64 2147483647
%2:sreg_64 = S_AND_B64 %0, %1, implicit-def $scc
SI_RETURN_TO_EPILOG %2
...
# FIXME: This could be folded, but we do not know if operand of S_AND_B64 is signed or unsigned
# and if it will be sign or zero extended.
---
name: fold_uint_32bit_literal_sgpr
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: fold_uint_32bit_literal_sgpr
; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 4294967295
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[DEF]], [[S_MOV_B64_]], implicit-def $scc
; GCN-NEXT: SI_RETURN_TO_EPILOG [[S_AND_B64_]]
%0:sreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64 4294967295
%2:sreg_64 = S_AND_B64 %0, %1, implicit-def $scc
SI_RETURN_TO_EPILOG %2
...
---
name: no_fold_v2fp_64bit_literal_sgpr
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: no_fold_v2fp_64bit_literal_sgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 4629700418019000320, implicit $exec
; GCN-NEXT: [[V_PK_ADD_F32_:%[0-9]+]]:vreg_64 = V_PK_ADD_F32 0, [[DEF]], 0, [[V_MOV_B]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_PK_ADD_F32_]]
%0:vreg_64 = IMPLICIT_DEF
%1:vreg_64 = V_MOV_B64_PSEUDO 4629700418019000320, implicit $exec
%2:vreg_64 = V_PK_ADD_F32 0, %0, 0, %1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
SI_RETURN_TO_EPILOG %2
...
---
name: fold_v2fp_32bit_literal_sgpr
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: fold_v2fp_32bit_literal_sgpr
; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; GCN-NEXT: [[V_PK_ADD_F32_:%[0-9]+]]:vreg_64 = V_PK_ADD_F32 0, [[DEF]], 0, 1065353216, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: SI_RETURN_TO_EPILOG [[V_PK_ADD_F32_]]
%0:vreg_64 = IMPLICIT_DEF
%1:vreg_64 = V_MOV_B64_PSEUDO 1065353216, implicit $exec
%2:vreg_64 = V_PK_ADD_F32 0, %0, 0, %1, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
SI_RETURN_TO_EPILOG %2
...
|
