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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
# Do not use inline constants for f16 pseudo scalar transcendentals.
# But allow literal constants.
---
name: exp_f16_imm
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: exp_f16_imm
; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
; GCN-NEXT: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: exp_f16_literal
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: exp_f16_literal
; GCN: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: log_f16_imm
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: log_f16_imm
; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
; GCN-NEXT: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: log_f16_literal
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: log_f16_literal
; GCN: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: rcp_f16_imm
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rcp_f16_imm
; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
; GCN-NEXT: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: rcp_f16_literal
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rcp_f16_literal
; GCN: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: rsq_f16_imm
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rsq_f16_imm
; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
; GCN-NEXT: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: rsq_f16_literal
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rsq_f16_literal
; GCN: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: sqrt_f16_imm
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: sqrt_f16_imm
; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
; GCN-NEXT: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
---
name: sqrt_f16_literal
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: sqrt_f16_literal
; GCN: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
|
