File: intrinsic-insgr2vr.ll

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llvm-toolchain-19 1%3A19.1.7-3
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32)

define <8 x i32> @lasx_xvinsgr2vr_w(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvinsgr2vr_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    ori $a0, $zero, 1
; CHECK-NEXT:    xvinsgr2vr.w $xr0, $a0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32> %va, i32 1, i32 1)
  ret <8 x i32> %res
}

declare <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64>, i64, i32)

define <4 x i64> @lasx_xvinsgr2vr_d(<4 x i64> %va) nounwind {
; CHECK-LABEL: lasx_xvinsgr2vr_d:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    ori $a0, $zero, 1
; CHECK-NEXT:    xvinsgr2vr.d $xr0, $a0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64> %va, i64 1, i32 1)
  ret <4 x i64> %res
}