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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvrepl128vei.b(<32 x i8>, i32)
define <32 x i8> @lasx_xvrepl128vei_b(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_xvrepl128vei_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvrepl128vei.b $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <32 x i8> @llvm.loongarch.lasx.xvrepl128vei.b(<32 x i8> %va, i32 1)
ret <32 x i8> %res
}
declare <16 x i16> @llvm.loongarch.lasx.xvrepl128vei.h(<16 x i16>, i32)
define <16 x i16> @lasx_xvrepl128vei_h(<16 x i16> %va) nounwind {
; CHECK-LABEL: lasx_xvrepl128vei_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvrepl128vei.h $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <16 x i16> @llvm.loongarch.lasx.xvrepl128vei.h(<16 x i16> %va, i32 1)
ret <16 x i16> %res
}
declare <8 x i32> @llvm.loongarch.lasx.xvrepl128vei.w(<8 x i32>, i32)
define <8 x i32> @lasx_xvrepl128vei_w(<8 x i32> %va) nounwind {
; CHECK-LABEL: lasx_xvrepl128vei_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvrepl128vei.w $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <8 x i32> @llvm.loongarch.lasx.xvrepl128vei.w(<8 x i32> %va, i32 1)
ret <8 x i32> %res
}
declare <4 x i64> @llvm.loongarch.lasx.xvrepl128vei.d(<4 x i64>, i32)
define <4 x i64> @lasx_xvrepl128vei_d(<4 x i64> %va) nounwind {
; CHECK-LABEL: lasx_xvrepl128vei_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvrepl128vei.d $xr0, $xr0, 1
; CHECK-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvrepl128vei.d(<4 x i64> %va, i32 1)
ret <4 x i64> %res
}
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