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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare i32 @llvm.loongarch.lasx.xbz.v(<32 x i8>)
define i32 @lasx_xbz_v(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_xbz_v:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvseteqz.v $fcc0, $xr0
; CHECK-NEXT: bcnez $fcc0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 0
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 1
; CHECK-NEXT: ret
entry:
%res = call i32 @llvm.loongarch.lasx.xbz.v(<32 x i8> %va)
ret i32 %res
}
declare i32 @llvm.loongarch.lasx.xbnz.v(<32 x i8>)
define i32 @lasx_xbnz_v(<32 x i8> %va) nounwind {
; CHECK-LABEL: lasx_xbnz_v:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvsetnez.v $fcc0, $xr0
; CHECK-NEXT: bcnez $fcc0, .LBB1_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 0
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: # %entry
; CHECK-NEXT: addi.w $a0, $zero, 1
; CHECK-NEXT: ret
entry:
%res = call i32 @llvm.loongarch.lasx.xbnz.v(<32 x i8> %va)
ret i32 %res
}
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