1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @ctpop_v16i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: ctpop_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vpcnt.b $vr0, $vr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
%v = load <16 x i8>, ptr %src
%res = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %v)
store <16 x i8> %res, ptr %dst
ret void
}
define void @ctpop_v8i16(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: ctpop_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vpcnt.h $vr0, $vr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
%v = load <8 x i16>, ptr %src
%res = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %v)
store <8 x i16> %res, ptr %dst
ret void
}
define void @ctpop_v4i32(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: ctpop_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vpcnt.w $vr0, $vr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
%v = load <4 x i32>, ptr %src
%res = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %v)
store <4 x i32> %res, ptr %dst
ret void
}
define void @ctpop_v2i64(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: ctpop_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vpcnt.d $vr0, $vr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
%v = load <2 x i64>, ptr %src
%res = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %v)
store <2 x i64> %res, ptr %dst
ret void
}
define void @ctlz_v16i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: ctlz_v16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vclz.b $vr0, $vr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
%v = load <16 x i8>, ptr %src
%res = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %v, i1 false)
store <16 x i8> %res, ptr %dst
ret void
}
define void @ctlz_v8i16(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: ctlz_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vclz.h $vr0, $vr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
%v = load <8 x i16>, ptr %src
%res = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %v, i1 false)
store <8 x i16> %res, ptr %dst
ret void
}
define void @ctlz_v4i32(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: ctlz_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vclz.w $vr0, $vr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
%v = load <4 x i32>, ptr %src
%res = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %v, i1 false)
store <4 x i32> %res, ptr %dst
ret void
}
define void @ctlz_v2i64(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: ctlz_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vld $vr0, $a0, 0
; CHECK-NEXT: vclz.d $vr0, $vr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
%v = load <2 x i64>, ptr %src
%res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %v, i1 false)
store <2 x i64> %res, ptr %dst
ret void
}
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1)
declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1)
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1)
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1)
|
