1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vmaddwev.h.b(<8 x i16>, <16 x i8>, <16 x i8>)
define <8 x i16> @lsx_vmaddwev_h_b(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_h_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.h.b $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <8 x i16> @llvm.loongarch.lsx.vmaddwev.h.b(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc)
ret <8 x i16> %res
}
declare <4 x i32> @llvm.loongarch.lsx.vmaddwev.w.h(<4 x i32>, <8 x i16>, <8 x i16>)
define <4 x i32> @lsx_vmaddwev_w_h(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_w_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.w.h $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <4 x i32> @llvm.loongarch.lsx.vmaddwev.w.h(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc)
ret <4 x i32> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwev.d.w(<2 x i64>, <4 x i32>, <4 x i32>)
define <2 x i64> @lsx_vmaddwev_d_w(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_d_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.d.w $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwev.d.w(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc)
ret <2 x i64> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwev.q.d(<2 x i64>, <2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vmaddwev_q_d(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_q_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.q.d $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwev.q.d(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc)
ret <2 x i64> %res
}
declare <8 x i16> @llvm.loongarch.lsx.vmaddwev.h.bu(<8 x i16>, <16 x i8>, <16 x i8>)
define <8 x i16> @lsx_vmaddwev_h_bu(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_h_bu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.h.bu $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <8 x i16> @llvm.loongarch.lsx.vmaddwev.h.bu(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc)
ret <8 x i16> %res
}
declare <4 x i32> @llvm.loongarch.lsx.vmaddwev.w.hu(<4 x i32>, <8 x i16>, <8 x i16>)
define <4 x i32> @lsx_vmaddwev_w_hu(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_w_hu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.w.hu $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <4 x i32> @llvm.loongarch.lsx.vmaddwev.w.hu(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc)
ret <4 x i32> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwev.d.wu(<2 x i64>, <4 x i32>, <4 x i32>)
define <2 x i64> @lsx_vmaddwev_d_wu(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_d_wu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.d.wu $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwev.d.wu(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc)
ret <2 x i64> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwev.q.du(<2 x i64>, <2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vmaddwev_q_du(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_q_du:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.q.du $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwev.q.du(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc)
ret <2 x i64> %res
}
declare <8 x i16> @llvm.loongarch.lsx.vmaddwev.h.bu.b(<8 x i16>, <16 x i8>, <16 x i8>)
define <8 x i16> @lsx_vmaddwev_h_bu_b(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_h_bu_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.h.bu.b $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <8 x i16> @llvm.loongarch.lsx.vmaddwev.h.bu.b(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc)
ret <8 x i16> %res
}
declare <4 x i32> @llvm.loongarch.lsx.vmaddwev.w.hu.h(<4 x i32>, <8 x i16>, <8 x i16>)
define <4 x i32> @lsx_vmaddwev_w_hu_h(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_w_hu_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.w.hu.h $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <4 x i32> @llvm.loongarch.lsx.vmaddwev.w.hu.h(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc)
ret <4 x i32> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwev.d.wu.w(<2 x i64>, <4 x i32>, <4 x i32>)
define <2 x i64> @lsx_vmaddwev_d_wu_w(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_d_wu_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.d.wu.w $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwev.d.wu.w(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc)
ret <2 x i64> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwev.q.du.d(<2 x i64>, <2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vmaddwev_q_du_d(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwev_q_du_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwev.q.du.d $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwev.q.du.d(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc)
ret <2 x i64> %res
}
declare <8 x i16> @llvm.loongarch.lsx.vmaddwod.h.b(<8 x i16>, <16 x i8>, <16 x i8>)
define <8 x i16> @lsx_vmaddwod_h_b(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_h_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.h.b $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <8 x i16> @llvm.loongarch.lsx.vmaddwod.h.b(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc)
ret <8 x i16> %res
}
declare <4 x i32> @llvm.loongarch.lsx.vmaddwod.w.h(<4 x i32>, <8 x i16>, <8 x i16>)
define <4 x i32> @lsx_vmaddwod_w_h(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_w_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.w.h $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <4 x i32> @llvm.loongarch.lsx.vmaddwod.w.h(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc)
ret <4 x i32> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwod.d.w(<2 x i64>, <4 x i32>, <4 x i32>)
define <2 x i64> @lsx_vmaddwod_d_w(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_d_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.d.w $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwod.d.w(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc)
ret <2 x i64> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwod.q.d(<2 x i64>, <2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vmaddwod_q_d(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_q_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.q.d $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwod.q.d(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc)
ret <2 x i64> %res
}
declare <8 x i16> @llvm.loongarch.lsx.vmaddwod.h.bu(<8 x i16>, <16 x i8>, <16 x i8>)
define <8 x i16> @lsx_vmaddwod_h_bu(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_h_bu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.h.bu $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <8 x i16> @llvm.loongarch.lsx.vmaddwod.h.bu(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc)
ret <8 x i16> %res
}
declare <4 x i32> @llvm.loongarch.lsx.vmaddwod.w.hu(<4 x i32>, <8 x i16>, <8 x i16>)
define <4 x i32> @lsx_vmaddwod_w_hu(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_w_hu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.w.hu $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <4 x i32> @llvm.loongarch.lsx.vmaddwod.w.hu(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc)
ret <4 x i32> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwod.d.wu(<2 x i64>, <4 x i32>, <4 x i32>)
define <2 x i64> @lsx_vmaddwod_d_wu(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_d_wu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.d.wu $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwod.d.wu(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc)
ret <2 x i64> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwod.q.du(<2 x i64>, <2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vmaddwod_q_du(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_q_du:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.q.du $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwod.q.du(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc)
ret <2 x i64> %res
}
declare <8 x i16> @llvm.loongarch.lsx.vmaddwod.h.bu.b(<8 x i16>, <16 x i8>, <16 x i8>)
define <8 x i16> @lsx_vmaddwod_h_bu_b(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_h_bu_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.h.bu.b $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <8 x i16> @llvm.loongarch.lsx.vmaddwod.h.bu.b(<8 x i16> %va, <16 x i8> %vb, <16 x i8> %vc)
ret <8 x i16> %res
}
declare <4 x i32> @llvm.loongarch.lsx.vmaddwod.w.hu.h(<4 x i32>, <8 x i16>, <8 x i16>)
define <4 x i32> @lsx_vmaddwod_w_hu_h(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_w_hu_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.w.hu.h $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <4 x i32> @llvm.loongarch.lsx.vmaddwod.w.hu.h(<4 x i32> %va, <8 x i16> %vb, <8 x i16> %vc)
ret <4 x i32> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwod.d.wu.w(<2 x i64>, <4 x i32>, <4 x i32>)
define <2 x i64> @lsx_vmaddwod_d_wu_w(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_d_wu_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.d.wu.w $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwod.d.wu.w(<2 x i64> %va, <4 x i32> %vb, <4 x i32> %vc)
ret <2 x i64> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vmaddwod.q.du.d(<2 x i64>, <2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vmaddwod_q_du_d(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc) nounwind {
; CHECK-LABEL: lsx_vmaddwod_q_du_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmaddwod.q.du.d $vr0, $vr1, $vr2
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vmaddwod.q.du.d(<2 x i64> %va, <2 x i64> %vb, <2 x i64> %vc)
ret <2 x i64> %res
}
|
