1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @sub_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: sub_v16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: vsub.b $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <16 x i8>, ptr %a0
%v1 = load <16 x i8>, ptr %a1
%v2 = sub <16 x i8> %v0, %v1
store <16 x i8> %v2, ptr %res
ret void
}
define void @sub_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: sub_v8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: vsub.h $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <8 x i16>, ptr %a0
%v1 = load <8 x i16>, ptr %a1
%v2 = sub <8 x i16> %v0, %v1
store <8 x i16> %v2, ptr %res
ret void
}
define void @sub_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: sub_v4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: vsub.w $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x i32>, ptr %a0
%v1 = load <4 x i32>, ptr %a1
%v2 = sub <4 x i32> %v0, %v1
store <4 x i32> %v2, ptr %res
ret void
}
define void @sub_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: sub_v2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vld $vr1, $a2, 0
; CHECK-NEXT: vsub.d $vr0, $vr0, $vr1
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <2 x i64>, ptr %a0
%v1 = load <2 x i64>, ptr %a1
%v2 = sub <2 x i64> %v0, %v1
store <2 x i64> %v2, ptr %res
ret void
}
define void @sub_v16i8_31(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: sub_v16i8_31:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vsubi.bu $vr0, $vr0, 31
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <16 x i8>, ptr %a0
%v1 = sub <16 x i8> %v0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>
store <16 x i8> %v1, ptr %res
ret void
}
define void @sub_v8i16_31(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: sub_v8i16_31:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vsubi.hu $vr0, $vr0, 31
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <8 x i16>, ptr %a0
%v1 = sub <8 x i16> %v0, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>
store <8 x i16> %v1, ptr %res
ret void
}
define void @sub_v4i32_31(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: sub_v4i32_31:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vsubi.wu $vr0, $vr0, 31
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x i32>, ptr %a0
%v1 = sub <4 x i32> %v0, <i32 31, i32 31, i32 31, i32 31>
store <4 x i32> %v1, ptr %res
ret void
}
define void @sub_v2i64_31(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: sub_v2i64_31:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vld $vr0, $a1, 0
; CHECK-NEXT: vsubi.du $vr0, $vr0, 31
; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <2 x i64>, ptr %a0
%v1 = sub <2 x i64> %v0, <i64 31, i64 31>
store <2 x i64> %v1, ptr %res
ret void
}
|
