1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
@float_align1 = common global float 0.000000e+00, align 1
@float_align8 = common global float 0.000000e+00, align 8
@i32_align2 = common global i32 0, align 2
define float @load_float_align1() {
entry:
%0 = load float, ptr @float_align1, align 1
ret float %0
}
define float @load_float_align8() {
entry:
%0 = load float, ptr @float_align8, align 8
ret float %0
}
define i32 @load_i32_align2() {
entry:
%0 = load i32, ptr @i32_align2, align 2
ret i32 %0
}
...
---
name: load_float_align1
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32R6-LABEL: name: load_float_align1
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align1
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
; MIPS32R6: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load (s32) from @float_align1, align 1)
; MIPS32R6: $f0 = COPY [[LWC1_]]
; MIPS32R6: RetRA implicit $f0
%1:gprb(p0) = G_GLOBAL_VALUE @float_align1
%0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @float_align1, align 1)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_float_align8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32R6-LABEL: name: load_float_align8
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @float_align8
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8
; MIPS32R6: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load (s32) from @float_align8, align 8)
; MIPS32R6: $f0 = COPY [[LWC1_]]
; MIPS32R6: RetRA implicit $f0
%1:gprb(p0) = G_GLOBAL_VALUE @float_align8
%0:fprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @float_align8, align 8)
$f0 = COPY %0(s32)
RetRA implicit $f0
...
---
name: load_i32_align2
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32R6-LABEL: name: load_i32_align2
; MIPS32R6: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) @i32_align2
; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
; MIPS32R6: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load (s32) from @i32_align2, align 2)
; MIPS32R6: $v0 = COPY [[LW]]
; MIPS32R6: RetRA implicit $v0
%1:gprb(p0) = G_GLOBAL_VALUE @i32_align2
%0:gprb(s32) = G_LOAD %1(p0) :: (dereferenceable load (s32) from @i32_align2, align 2)
$v0 = COPY %0(s32)
RetRA implicit $v0
...
|
