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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
---
name: select_i32
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x12
; RV32I-LABEL: name: select_i32
; RV32I: liveins: $x10, $x11, $x12
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x12
; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
; RV32I-NEXT: PseudoRET implicit $x10
%3:_(s32) = COPY $x10
%4:_(s32) = COPY $x11
%5:_(s32) = COPY $x12
%12:_(s32) = G_CONSTANT i32 1
%11:_(s32) = G_AND %3, %12
%10:_(s32) = G_SELECT %11(s32), %4, %5
$x10 = COPY %10(s32)
PseudoRET implicit $x10
...
---
name: select_ptr
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x12
; RV32I-LABEL: name: select_ptr
; RV32I: liveins: $x10, $x11, $x12
; RV32I-NEXT: {{ $}}
; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $x12
; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; RV32I-NEXT: $x10 = COPY [[SELECT]](p0)
; RV32I-NEXT: PseudoRET implicit $x10
%3:_(s32) = COPY $x10
%4:_(p0) = COPY $x11
%5:_(p0) = COPY $x12
%12:_(s32) = G_CONSTANT i32 1
%11:_(s32) = G_AND %3, %12
%10:_(p0) = G_SELECT %11(s32), %4, %5
$x10 = COPY %10(p0)
PseudoRET implicit $x10
...
|
