1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvksed \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvksed \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
declare <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i32(
<vscale x 4 x i32>,
<vscale x 4 x i32>,
iXLen,
iXLen)
define <vscale x 4 x i32> @intrinsic_vsm4k_vi_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsm4k_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vsm4k.vi v8, v8, 2
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsm4k.nxv4i32.i32(
<vscale x 4 x i32> undef,
<vscale x 4 x i32> %0,
iXLen 2,
iXLen %1)
ret <vscale x 4 x i32> %a
}
declare <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i32(
<vscale x 8 x i32>,
<vscale x 8 x i32>,
iXLen,
iXLen)
define <vscale x 8 x i32> @intrinsic_vsm4k_vi_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsm4k_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vsm4k.vi v8, v8, 2
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsm4k.nxv8i32.i32(
<vscale x 8 x i32> undef,
<vscale x 8 x i32> %0,
iXLen 2,
iXLen %1)
ret <vscale x 8 x i32> %a
}
declare <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i32(
<vscale x 16 x i32>,
<vscale x 16 x i32>,
iXLen,
iXLen)
define <vscale x 16 x i32> @intrinsic_vsm4k_vi_nxv16i32_i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vsm4k_vi_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vsm4k.vi v8, v8, 2
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsm4k.nxv16i32.i32(
<vscale x 16 x i32> undef,
<vscale x 16 x i32> %0,
iXLen 2,
iXLen %1)
ret <vscale x 16 x i32> %a
}
|
