1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s
define i8 @test_i8(i8 %a) nounwind {
; CHECK-LABEL: test_i8:
; CHECK: @ %bb.0:
; CHECK-NEXT: sxtb r1, r0
; CHECK-NEXT: asrs r1, r1, #7
; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: subs r0, r0, r1
; CHECK-NEXT: bx lr
%tmp1neg = sub i8 0, %a
%b = icmp sgt i8 %a, -1
%abs = select i1 %b, i8 %a, i8 %tmp1neg
ret i8 %abs
}
define i16 @test_i16(i16 %a) nounwind {
; CHECK-LABEL: test_i16:
; CHECK: @ %bb.0:
; CHECK-NEXT: sxth r1, r0
; CHECK-NEXT: asrs r1, r1, #15
; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: subs r0, r0, r1
; CHECK-NEXT: bx lr
%tmp1neg = sub i16 0, %a
%b = icmp sgt i16 %a, -1
%abs = select i1 %b, i16 %a, i16 %tmp1neg
ret i16 %abs
}
define i32 @test_i32(i32 %a) nounwind {
; CHECK-LABEL: test_i32:
; CHECK: @ %bb.0:
; CHECK-NEXT: asrs r1, r0, #31
; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: subs r0, r0, r1
; CHECK-NEXT: bx lr
%tmp1neg = sub i32 0, %a
%b = icmp sgt i32 %a, -1
%abs = select i1 %b, i32 %a, i32 %tmp1neg
ret i32 %abs
}
define i64 @test_i64(i64 %a) nounwind {
; CHECK-LABEL: test_i64:
; CHECK: @ %bb.0:
; CHECK-NEXT: asrs r2, r1, #31
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: subs r0, r0, r2
; CHECK-NEXT: sbcs r1, r2
; CHECK-NEXT: bx lr
%tmp1neg = sub i64 0, %a
%b = icmp sgt i64 %a, -1
%abs = select i1 %b, i64 %a, i64 %tmp1neg
ret i64 %abs
}
|
