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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX
define void @PR72539(<8 x i32> %insertelement){
; SSE-LABEL: PR72539:
; SSE: # %bb.0:
; SSE-NEXT: xorb $7, 0
; SSE-NEXT: retq
;
; AVX-LABEL: PR72539:
; AVX: # %bb.0:
; AVX-NEXT: movzbl {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %eax
; AVX-NEXT: xorb %al, 0
; AVX-NEXT: retq
%load671 = load i8, ptr addrspace(1) null, align 1
%shufflevector = shufflevector <8 x i32> %insertelement, <8 x i32> zeroinitializer, <8 x i32> zeroinitializer
%xor68 = xor <8 x i32> %shufflevector, <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
%call69 = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %xor68)
%trunc70 = trunc i32 %call69 to i8
%xor71 = xor i8 %load671, %trunc70
store i8 %xor71, ptr addrspace(1) null, align 1
ret void
}
declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)
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