1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefix=X86-SSE2
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=i686-unknown -mattr=avx | FileCheck %s --check-prefixes=X86-AVX,X86-AVX1
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=i686-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X86-AVX,AVX512-i32
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=i686-unknown -mattr=avx512dq,avx512vl | FileCheck %s --check-prefixes=X86-AVX,AVX512-i32
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=x86_64-unknown -mattr=avx | FileCheck %s --check-prefixes=X64-AVX-i32,X64-AVX1-i32
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64-AVX-i32,AVX512-i32
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=x86_64-unknown -mattr=avx512dq,avx512vl | FileCheck %s --check-prefixes=X64-AVX-i32,AVX512-i32
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=x86_64-unknown -mattr=avx | FileCheck %s --check-prefixes=X64-AVX-i64,X64-AVX1-i64
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64-AVX-i64,AVX512-i64
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=x86_64-unknown -mattr=avx512dq,avx512vl | FileCheck %s --check-prefixes=X64-AVX-i64,AVX512DQ-i64
define <1 x iXLen> @lrint_v1f32(<1 x float> %x) {
; X86-SSE2-LABEL: lrint_v1f32:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: cvtss2si {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: retl
;
; X86-AVX-LABEL: lrint_v1f32:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vcvtss2si {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: retl
;
; X64-AVX-i32-LABEL: lrint_v1f32:
; X64-AVX-i32: # %bb.0:
; X64-AVX-i32-NEXT: vcvtss2si %xmm0, %eax
; X64-AVX-i32-NEXT: retq
;
; X64-AVX-i64-LABEL: lrint_v1f32:
; X64-AVX-i64: # %bb.0:
; X64-AVX-i64-NEXT: vcvtss2si %xmm0, %rax
; X64-AVX-i64-NEXT: retq
%a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f32(<1 x float> %x)
ret <1 x iXLen> %a
}
declare <1 x iXLen> @llvm.lrint.v1iXLen.v1f32(<1 x float>)
define <2 x iXLen> @lrint_v2f32(<2 x float> %x) {
; X86-SSE2-LABEL: lrint_v2f32:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: cvtps2dq %xmm0, %xmm0
; X86-SSE2-NEXT: retl
;
; X86-AVX-LABEL: lrint_v2f32:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vcvtps2dq %xmm0, %xmm0
; X86-AVX-NEXT: retl
;
; X64-AVX-i32-LABEL: lrint_v2f32:
; X64-AVX-i32: # %bb.0:
; X64-AVX-i32-NEXT: vcvtps2dq %xmm0, %xmm0
; X64-AVX-i32-NEXT: retq
;
; X64-AVX1-i64-LABEL: lrint_v2f32:
; X64-AVX1-i64: # %bb.0:
; X64-AVX1-i64-NEXT: vcvtss2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm1
; X64-AVX1-i64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm0
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; X64-AVX1-i64-NEXT: retq
;
; AVX512-i64-LABEL: lrint_v2f32:
; AVX512-i64: # %bb.0:
; AVX512-i64-NEXT: vcvtss2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm1
; AVX512-i64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; AVX512-i64-NEXT: vcvtss2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm0
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX512-i64-NEXT: retq
;
; AVX512DQ-i64-LABEL: lrint_v2f32:
; AVX512DQ-i64: # %bb.0:
; AVX512DQ-i64-NEXT: vcvtps2qq %xmm0, %xmm0
; AVX512DQ-i64-NEXT: retq
%a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f32(<2 x float> %x)
ret <2 x iXLen> %a
}
declare <2 x iXLen> @llvm.lrint.v2iXLen.v2f32(<2 x float>)
define <4 x iXLen> @lrint_v4f32(<4 x float> %x) {
; X86-SSE2-LABEL: lrint_v4f32:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: cvtps2dq %xmm0, %xmm0
; X86-SSE2-NEXT: retl
;
; X86-AVX-LABEL: lrint_v4f32:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vcvtps2dq %xmm0, %xmm0
; X86-AVX-NEXT: retl
;
; X64-AVX-i32-LABEL: lrint_v4f32:
; X64-AVX-i32: # %bb.0:
; X64-AVX-i32-NEXT: vcvtps2dq %xmm0, %xmm0
; X64-AVX-i32-NEXT: retq
;
; X64-AVX1-i64-LABEL: lrint_v4f32:
; X64-AVX1-i64: # %bb.0:
; X64-AVX1-i64-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm1, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm1
; X64-AVX1-i64-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm2, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm2
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm2
; X64-AVX1-i64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm0
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; X64-AVX1-i64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X64-AVX1-i64-NEXT: retq
;
; AVX512-i64-LABEL: lrint_v4f32:
; AVX512-i64: # %bb.0:
; AVX512-i64-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
; AVX512-i64-NEXT: vcvtss2si %xmm1, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm1
; AVX512-i64-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX512-i64-NEXT: vcvtss2si %xmm2, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm2
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512-i64-NEXT: vcvtss2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm2
; AVX512-i64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; AVX512-i64-NEXT: vcvtss2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm0
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; AVX512-i64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX512-i64-NEXT: retq
;
; AVX512DQ-i64-LABEL: lrint_v4f32:
; AVX512DQ-i64: # %bb.0:
; AVX512DQ-i64-NEXT: vcvtps2qq %xmm0, %ymm0
; AVX512DQ-i64-NEXT: retq
%a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f32(<4 x float> %x)
ret <4 x iXLen> %a
}
declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f32(<4 x float>)
define <8 x iXLen> @lrint_v8f32(<8 x float> %x) {
; X86-SSE2-LABEL: lrint_v8f32:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: cvtps2dq %xmm0, %xmm0
; X86-SSE2-NEXT: cvtps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: retl
;
; X86-AVX-LABEL: lrint_v8f32:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vcvtps2dq %ymm0, %ymm0
; X86-AVX-NEXT: retl
;
; X64-AVX-i32-LABEL: lrint_v8f32:
; X64-AVX-i32: # %bb.0:
; X64-AVX-i32-NEXT: vcvtps2dq %ymm0, %ymm0
; X64-AVX-i32-NEXT: retq
;
; X64-AVX1-i64-LABEL: lrint_v8f32:
; X64-AVX1-i64: # %bb.0:
; X64-AVX1-i64-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm1, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm1
; X64-AVX1-i64-NEXT: vshufpd {{.*#+}} xmm2 = xmm0[1,0]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm2, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm2
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm2
; X64-AVX1-i64-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm3, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm3
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; X64-AVX1-i64-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm2
; X64-AVX1-i64-NEXT: vextractf128 $1, %ymm0, %xmm0
; X64-AVX1-i64-NEXT: vshufps {{.*#+}} xmm1 = xmm0[3,3,3,3]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm1, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm1
; X64-AVX1-i64-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm3, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm3
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm1[0]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm3
; X64-AVX1-i64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X64-AVX1-i64-NEXT: vcvtss2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm0
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
; X64-AVX1-i64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
; X64-AVX1-i64-NEXT: vmovaps %ymm2, %ymm0
; X64-AVX1-i64-NEXT: retq
;
; AVX512-i64-LABEL: lrint_v8f32:
; AVX512-i64: # %bb.0:
; AVX512-i64-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512-i64-NEXT: vshufps {{.*#+}} xmm2 = xmm1[3,3,3,3]
; AVX512-i64-NEXT: vcvtss2si %xmm2, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm2
; AVX512-i64-NEXT: vshufpd {{.*#+}} xmm3 = xmm1[1,0]
; AVX512-i64-NEXT: vcvtss2si %xmm3, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm3
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512-i64-NEXT: vcvtss2si %xmm1, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm3
; AVX512-i64-NEXT: vmovshdup {{.*#+}} xmm1 = xmm1[1,1,3,3]
; AVX512-i64-NEXT: vcvtss2si %xmm1, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm1
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm1[0]
; AVX512-i64-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; AVX512-i64-NEXT: vshufps {{.*#+}} xmm2 = xmm0[3,3,3,3]
; AVX512-i64-NEXT: vcvtss2si %xmm2, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm2
; AVX512-i64-NEXT: vshufpd {{.*#+}} xmm3 = xmm0[1,0]
; AVX512-i64-NEXT: vcvtss2si %xmm3, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm3
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512-i64-NEXT: vcvtss2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm3
; AVX512-i64-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; AVX512-i64-NEXT: vcvtss2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm0
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
; AVX512-i64-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX512-i64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512-i64-NEXT: retq
;
; AVX512DQ-i64-LABEL: lrint_v8f32:
; AVX512DQ-i64: # %bb.0:
; AVX512DQ-i64-NEXT: vcvtps2qq %ymm0, %zmm0
; AVX512DQ-i64-NEXT: retq
%a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f32(<8 x float> %x)
ret <8 x iXLen> %a
}
declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f32(<8 x float>)
define <16 x iXLen> @lrint_v16iXLen_v16f32(<16 x float> %x) {
%a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f32(<16 x float> %x)
ret <16 x iXLen> %a
}
declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f32(<16 x float>)
define <1 x iXLen> @lrint_v1f64(<1 x double> %x) {
; X86-SSE2-LABEL: lrint_v1f64:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: cvtsd2si {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: retl
;
; X86-AVX-LABEL: lrint_v1f64:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vcvtsd2si {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: retl
;
; X64-AVX-i32-LABEL: lrint_v1f64:
; X64-AVX-i32: # %bb.0:
; X64-AVX-i32-NEXT: vcvtsd2si %xmm0, %eax
; X64-AVX-i32-NEXT: retq
;
; X64-AVX-i64-LABEL: lrint_v1f64:
; X64-AVX-i64: # %bb.0:
; X64-AVX-i64-NEXT: vcvtsd2si %xmm0, %rax
; X64-AVX-i64-NEXT: retq
%a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f64(<1 x double> %x)
ret <1 x iXLen> %a
}
declare <1 x iXLen> @llvm.lrint.v1iXLen.v1f64(<1 x double>)
define <2 x iXLen> @lrint_v2f64(<2 x double> %x) {
; X86-SSE2-LABEL: lrint_v2f64:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: cvtsd2si %xmm0, %eax
; X86-SSE2-NEXT: movd %eax, %xmm1
; X86-SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; X86-SSE2-NEXT: cvtsd2si %xmm0, %eax
; X86-SSE2-NEXT: movd %eax, %xmm0
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; X86-SSE2-NEXT: movdqa %xmm1, %xmm0
; X86-SSE2-NEXT: retl
;
; X86-AVX-LABEL: lrint_v2f64:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
; X86-AVX-NEXT: vcvtsd2si %xmm1, %eax
; X86-AVX-NEXT: vcvtsd2si %xmm0, %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
; X86-AVX-NEXT: retl
;
; X64-AVX-i32-LABEL: lrint_v2f64:
; X64-AVX-i32: # %bb.0:
; X64-AVX-i32-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
; X64-AVX-i32-NEXT: vcvtsd2si %xmm1, %eax
; X64-AVX-i32-NEXT: vcvtsd2si %xmm0, %ecx
; X64-AVX-i32-NEXT: vmovd %ecx, %xmm0
; X64-AVX-i32-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
; X64-AVX-i32-NEXT: retq
;
; X64-AVX1-i64-LABEL: lrint_v2f64:
; X64-AVX1-i64: # %bb.0:
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm1
; X64-AVX1-i64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm0
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; X64-AVX1-i64-NEXT: retq
;
; AVX512-i64-LABEL: lrint_v2f64:
; AVX512-i64: # %bb.0:
; AVX512-i64-NEXT: vcvtsd2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm1
; AVX512-i64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-i64-NEXT: vcvtsd2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm0
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX512-i64-NEXT: retq
;
; AVX512DQ-i64-LABEL: lrint_v2f64:
; AVX512DQ-i64: # %bb.0:
; AVX512DQ-i64-NEXT: vcvtpd2qq %xmm0, %xmm0
; AVX512DQ-i64-NEXT: retq
%a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f64(<2 x double> %x)
ret <2 x iXLen> %a
}
declare <2 x iXLen> @llvm.lrint.v2iXLen.v2f64(<2 x double>)
define <4 x iXLen> @lrint_v4f64(<4 x double> %x) {
; X86-SSE2-LABEL: lrint_v4f64:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: cvtsd2si %xmm1, %eax
; X86-SSE2-NEXT: movd %eax, %xmm2
; X86-SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; X86-SSE2-NEXT: cvtsd2si %xmm1, %eax
; X86-SSE2-NEXT: movd %eax, %xmm1
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; X86-SSE2-NEXT: cvtsd2si %xmm0, %eax
; X86-SSE2-NEXT: movd %eax, %xmm1
; X86-SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; X86-SSE2-NEXT: cvtsd2si %xmm0, %eax
; X86-SSE2-NEXT: movd %eax, %xmm0
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; X86-SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; X86-SSE2-NEXT: movdqa %xmm1, %xmm0
; X86-SSE2-NEXT: retl
;
; X86-AVX-LABEL: lrint_v4f64:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vcvtpd2dq %ymm0, %xmm0
; X86-AVX-NEXT: vzeroupper
; X86-AVX-NEXT: retl
;
; X64-AVX-i32-LABEL: lrint_v4f64:
; X64-AVX-i32: # %bb.0:
; X64-AVX-i32-NEXT: vcvtpd2dq %ymm0, %xmm0
; X64-AVX-i32-NEXT: vzeroupper
; X64-AVX-i32-NEXT: retq
;
; X64-AVX1-i64-LABEL: lrint_v4f64:
; X64-AVX1-i64: # %bb.0:
; X64-AVX1-i64-NEXT: vextractf128 $1, %ymm0, %xmm1
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm1, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm2
; X64-AVX1-i64-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1,0]
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm1, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm1
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm2
; X64-AVX1-i64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm0
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; X64-AVX1-i64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X64-AVX1-i64-NEXT: retq
;
; AVX512-i64-LABEL: lrint_v4f64:
; AVX512-i64: # %bb.0:
; AVX512-i64-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512-i64-NEXT: vcvtsd2si %xmm1, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm2
; AVX512-i64-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1,0]
; AVX512-i64-NEXT: vcvtsd2si %xmm1, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm1
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512-i64-NEXT: vcvtsd2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm2
; AVX512-i64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-i64-NEXT: vcvtsd2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm0
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; AVX512-i64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX512-i64-NEXT: retq
;
; AVX512DQ-i64-LABEL: lrint_v4f64:
; AVX512DQ-i64: # %bb.0:
; AVX512DQ-i64-NEXT: vcvtpd2qq %ymm0, %ymm0
; AVX512DQ-i64-NEXT: retq
%a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f64(<4 x double> %x)
ret <4 x iXLen> %a
}
declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f64(<4 x double>)
define <8 x iXLen> @lrint_v8f64(<8 x double> %x) {
; X86-SSE2-LABEL: lrint_v8f64:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp
; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
; X86-SSE2-NEXT: .cfi_offset %ebp, -8
; X86-SSE2-NEXT: movl %esp, %ebp
; X86-SSE2-NEXT: .cfi_def_cfa_register %ebp
; X86-SSE2-NEXT: andl $-16, %esp
; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: movapd %xmm0, %xmm3
; X86-SSE2-NEXT: movapd 8(%ebp), %xmm4
; X86-SSE2-NEXT: cvtsd2si %xmm1, %eax
; X86-SSE2-NEXT: movd %eax, %xmm5
; X86-SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1,1]
; X86-SSE2-NEXT: cvtsd2si %xmm1, %eax
; X86-SSE2-NEXT: movd %eax, %xmm0
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm0[0],xmm5[1],xmm0[1]
; X86-SSE2-NEXT: cvtsd2si %xmm3, %eax
; X86-SSE2-NEXT: movd %eax, %xmm0
; X86-SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
; X86-SSE2-NEXT: cvtsd2si %xmm3, %eax
; X86-SSE2-NEXT: movd %eax, %xmm1
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm5[0]
; X86-SSE2-NEXT: cvtsd2si %xmm4, %eax
; X86-SSE2-NEXT: movd %eax, %xmm3
; X86-SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1,1]
; X86-SSE2-NEXT: cvtsd2si %xmm4, %eax
; X86-SSE2-NEXT: movd %eax, %xmm1
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; X86-SSE2-NEXT: cvtsd2si %xmm2, %eax
; X86-SSE2-NEXT: movd %eax, %xmm1
; X86-SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
; X86-SSE2-NEXT: cvtsd2si %xmm2, %eax
; X86-SSE2-NEXT: movd %eax, %xmm2
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; X86-SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp
; X86-SSE2-NEXT: .cfi_def_cfa %esp, 4
; X86-SSE2-NEXT: retl
;
; X86-AVX1-LABEL: lrint_v8f64:
; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vcvtpd2dq %ymm0, %xmm0
; X86-AVX1-NEXT: vcvtpd2dq %ymm1, %xmm1
; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-AVX1-NEXT: retl
;
; AVX512-i32-LABEL: lrint_v8f64:
; AVX512-i32: # %bb.0:
; AVX512-i32-NEXT: vcvtpd2dq %zmm0, %ymm0
; AVX512-i32-NEXT: ret{{[l|q]}}
;
; X64-AVX1-i32-LABEL: lrint_v8f64:
; X64-AVX1-i32: # %bb.0:
; X64-AVX1-i32-NEXT: vcvtpd2dq %ymm0, %xmm0
; X64-AVX1-i32-NEXT: vcvtpd2dq %ymm1, %xmm1
; X64-AVX1-i32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X64-AVX1-i32-NEXT: retq
;
; X64-AVX1-i64-LABEL: lrint_v8f64:
; X64-AVX1-i64: # %bb.0:
; X64-AVX1-i64-NEXT: vextractf128 $1, %ymm0, %xmm2
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm2, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm3
; X64-AVX1-i64-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm2, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm2
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm3
; X64-AVX1-i64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm0, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm0
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
; X64-AVX1-i64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; X64-AVX1-i64-NEXT: vextractf128 $1, %ymm1, %xmm2
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm2, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm3
; X64-AVX1-i64-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm2, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm2
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm1, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm3
; X64-AVX1-i64-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1,0]
; X64-AVX1-i64-NEXT: vcvtsd2si %xmm1, %rax
; X64-AVX1-i64-NEXT: vmovq %rax, %xmm1
; X64-AVX1-i64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm1[0]
; X64-AVX1-i64-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; X64-AVX1-i64-NEXT: retq
;
; AVX512-i64-LABEL: lrint_v8f64:
; AVX512-i64: # %bb.0:
; AVX512-i64-NEXT: vextractf32x4 $3, %zmm0, %xmm1
; AVX512-i64-NEXT: vcvtsd2si %xmm1, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm2
; AVX512-i64-NEXT: vshufpd {{.*#+}} xmm1 = xmm1[1,0]
; AVX512-i64-NEXT: vcvtsd2si %xmm1, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm1
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512-i64-NEXT: vextractf32x4 $2, %zmm0, %xmm2
; AVX512-i64-NEXT: vcvtsd2si %xmm2, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm3
; AVX512-i64-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]
; AVX512-i64-NEXT: vcvtsd2si %xmm2, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm2
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512-i64-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX512-i64-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX512-i64-NEXT: vcvtsd2si %xmm2, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm3
; AVX512-i64-NEXT: vshufpd {{.*#+}} xmm2 = xmm2[1,0]
; AVX512-i64-NEXT: vcvtsd2si %xmm2, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm2
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX512-i64-NEXT: vcvtsd2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm3
; AVX512-i64-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
; AVX512-i64-NEXT: vcvtsd2si %xmm0, %rax
; AVX512-i64-NEXT: vmovq %rax, %xmm0
; AVX512-i64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm3[0],xmm0[0]
; AVX512-i64-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX512-i64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512-i64-NEXT: retq
;
; AVX512DQ-i64-LABEL: lrint_v8f64:
; AVX512DQ-i64: # %bb.0:
; AVX512DQ-i64-NEXT: vcvtpd2qq %zmm0, %zmm0
; AVX512DQ-i64-NEXT: retq
%a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double> %x)
ret <8 x iXLen> %a
}
declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double>)
|
