1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -S -passes=gvn-hoist < %s | FileCheck %s
; Checking gvn-hoist in case of indirect branches.
%class.bar = type { ptr, ptr }
%class.base = type { ptr }
@bar = local_unnamed_addr global ptr null, align 8
@bar1 = local_unnamed_addr global ptr null, align 8
; Check that the bitcast is not hoisted because it is after an indirect call
define i32 @foo(ptr nocapture readonly %i) {
; CHECK-LABEL: define i32 @foo
; CHECK-SAME: (ptr nocapture readonly [[I:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_BAR:%.*]], align 8
; CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_BAR]], ptr [[AGG_TMP]], i64 0, i32 1
; CHECK-NEXT: [[Y:%.*]] = load ptr, ptr [[X]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4
; CHECK-NEXT: [[DOTOFF:%.*]] = add i32 [[TMP0]], -1
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[DOTOFF]], 2
; CHECK-NEXT: br i1 [[SWITCH]], label [[L1_PREHEADER:%.*]], label [[SW_DEFAULT:%.*]]
; CHECK: l1.preheader:
; CHECK-NEXT: [[B1:%.*]] = bitcast ptr [[Y]] to ptr
; CHECK-NEXT: br label [[L1:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr @bar, align 8
; CHECK-NEXT: [[CALL:%.*]] = tail call i32 [[TMP1]]()
; CHECK-NEXT: [[B2:%.*]] = bitcast ptr [[Y]] to ptr
; CHECK-NEXT: br label [[L1]]
; CHECK: sw.default:
; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr @bar1, align 8
; CHECK-NEXT: [[CALL2:%.*]] = tail call i32 [[TMP2]]()
; CHECK-NEXT: br label [[L1_PREHEADER]]
;
entry:
%agg.tmp = alloca %class.bar, align 8
%x= getelementptr inbounds %class.bar, ptr %agg.tmp, i64 0, i32 1
%y = load ptr, ptr %x, align 8
%0 = load i32, ptr %i, align 4
%.off = add i32 %0, -1
%switch = icmp ult i32 %.off, 2
br i1 %switch, label %l1.preheader, label %sw.default
l1.preheader: ; preds = %sw.default, %entry
%b1 = bitcast ptr %y to ptr
br label %l1
l1: ; preds = %l1.preheader, %l1
%1 = load ptr, ptr @bar, align 8
%call = tail call i32 %1()
%b2 = bitcast ptr %y to ptr
br label %l1
sw.default: ; preds = %entry
%2 = load ptr, ptr @bar1, align 8
%call2 = tail call i32 %2()
br label %l1.preheader
}
; Any instruction inside an infinite loop will not be hoisted because
; there is no path to exit of the function.
define i32 @foo1(ptr nocapture readonly %i) {
; CHECK-LABEL: define i32 @foo1
; CHECK-SAME: (ptr nocapture readonly [[I:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_BAR:%.*]], align 8
; CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_BAR]], ptr [[AGG_TMP]], i64 0, i32 1
; CHECK-NEXT: [[Y:%.*]] = load ptr, ptr [[X]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4
; CHECK-NEXT: [[DOTOFF:%.*]] = add i32 [[TMP0]], -1
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[DOTOFF]], 2
; CHECK-NEXT: br i1 [[SWITCH]], label [[L1_PREHEADER:%.*]], label [[SW_DEFAULT:%.*]]
; CHECK: l1.preheader:
; CHECK-NEXT: [[B1:%.*]] = bitcast ptr [[Y]] to ptr
; CHECK-NEXT: [[Y1:%.*]] = load ptr, ptr [[X]], align 8
; CHECK-NEXT: br label [[L1:%.*]]
; CHECK: l1:
; CHECK-NEXT: [[B2:%.*]] = bitcast ptr [[Y]] to ptr
; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr @bar, align 8
; CHECK-NEXT: [[Y2:%.*]] = load ptr, ptr [[X]], align 8
; CHECK-NEXT: [[CALL:%.*]] = tail call i32 [[TMP1]]()
; CHECK-NEXT: br label [[L1]]
; CHECK: sw.default:
; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr @bar1, align 8
; CHECK-NEXT: [[CALL2:%.*]] = tail call i32 [[TMP2]]()
; CHECK-NEXT: br label [[L1_PREHEADER]]
;
entry:
%agg.tmp = alloca %class.bar, align 8
%x= getelementptr inbounds %class.bar, ptr %agg.tmp, i64 0, i32 1
%y = load ptr, ptr %x, align 8
%0 = load i32, ptr %i, align 4
%.off = add i32 %0, -1
%switch = icmp ult i32 %.off, 2
br i1 %switch, label %l1.preheader, label %sw.default
l1.preheader: ; preds = %sw.default, %entry
%b1 = bitcast ptr %y to ptr
%y1 = load ptr, ptr %x, align 8
br label %l1
l1: ; preds = %l1.preheader, %l1
%b2 = bitcast ptr %y to ptr
%1 = load ptr, ptr @bar, align 8
%y2 = load ptr, ptr %x, align 8
%call = tail call i32 %1()
br label %l1
sw.default: ; preds = %entry
%2 = load ptr, ptr @bar1, align 8
%call2 = tail call i32 %2()
br label %l1.preheader
}
; Check that bitcast is hoisted even when one of them is partially redundant.
define i32 @test13(ptr %P, ptr %Ptr, ptr nocapture readonly %i) {
; CHECK-LABEL: define i32 @test13
; CHECK-SAME: (ptr [[P:%.*]], ptr [[PTR:%.*]], ptr nocapture readonly [[I:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_BAR:%.*]], align 8
; CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_BAR]], ptr [[AGG_TMP]], i64 0, i32 1
; CHECK-NEXT: [[Y:%.*]] = load ptr, ptr [[X]], align 8
; CHECK-NEXT: [[B2:%.*]] = bitcast ptr [[Y]] to ptr
; CHECK-NEXT: indirectbr ptr [[PTR]], [label [[BRBLOCK:%.*]], label %B2]
; CHECK: B2:
; CHECK-NEXT: store i32 4, ptr [[P]], align 4
; CHECK-NEXT: br label [[BRBLOCK]]
; CHECK: BrBlock:
; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[P]], align 4
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 42
; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]]
; CHECK: T:
; CHECK-NEXT: ret i32 123
; CHECK: F:
; CHECK-NEXT: ret i32 1422
;
entry:
%agg.tmp = alloca %class.bar, align 8
%x= getelementptr inbounds %class.bar, ptr %agg.tmp, i64 0, i32 1
%y = load ptr, ptr %x, align 8
indirectbr ptr %Ptr, [label %BrBlock, label %B2]
B2:
%b1 = bitcast ptr %y to ptr
store i32 4, ptr %P
br label %BrBlock
BrBlock:
%b2 = bitcast ptr %y to ptr
%L = load i32, ptr %P
%C = icmp eq i32 %L, 42
br i1 %C, label %T, label %F
T:
ret i32 123
F:
ret i32 1422
}
; Check that the bitcast is not hoisted because anticipability
; cannot be guaranteed here as one of the indirect branch targets
; do not have the bitcast instruction.
define i32 @test14(ptr %P, ptr %Ptr, ptr nocapture readonly %i) {
; CHECK-LABEL: define i32 @test14
; CHECK-SAME: (ptr [[P:%.*]], ptr [[PTR:%.*]], ptr nocapture readonly [[I:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_BAR:%.*]], align 8
; CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_BAR]], ptr [[AGG_TMP]], i64 0, i32 1
; CHECK-NEXT: [[Y:%.*]] = load ptr, ptr [[X]], align 8
; CHECK-NEXT: indirectbr ptr [[PTR]], [label [[BRBLOCK:%.*]], label [[B2:%.*]], label %T]
; CHECK: B2:
; CHECK-NEXT: [[B1:%.*]] = bitcast ptr [[Y]] to ptr
; CHECK-NEXT: store i32 4, ptr [[P]], align 4
; CHECK-NEXT: br label [[BRBLOCK]]
; CHECK: BrBlock:
; CHECK-NEXT: [[B2:%.*]] = bitcast ptr [[Y]] to ptr
; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[P]], align 4
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 42
; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]]
; CHECK: T:
; CHECK-NEXT: [[PI:%.*]] = load i32, ptr [[I]], align 4
; CHECK-NEXT: ret i32 [[PI]]
; CHECK: F:
; CHECK-NEXT: [[PL:%.*]] = load i32, ptr [[P]], align 4
; CHECK-NEXT: ret i32 [[PL]]
;
entry:
%agg.tmp = alloca %class.bar, align 8
%x= getelementptr inbounds %class.bar, ptr %agg.tmp, i64 0, i32 1
%y = load ptr, ptr %x, align 8
indirectbr ptr %Ptr, [label %BrBlock, label %B2, label %T]
B2:
%b1 = bitcast ptr %y to ptr
store i32 4, ptr %P
br label %BrBlock
BrBlock:
%b2 = bitcast ptr %y to ptr
%L = load i32, ptr %P
%C = icmp eq i32 %L, 42
br i1 %C, label %T, label %F
T:
%pi = load i32, ptr %i, align 4
ret i32 %pi
F:
%pl = load i32, ptr %P
ret i32 %pl
}
; Check that the bitcast is not hoisted because of a cycle
; due to indirect branches
define i32 @test16(ptr %P, ptr %Ptr, ptr nocapture readonly %i) {
; CHECK-LABEL: define i32 @test16
; CHECK-SAME: (ptr [[P:%.*]], ptr [[PTR:%.*]], ptr nocapture readonly [[I:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca [[CLASS_BAR:%.*]], align 8
; CHECK-NEXT: [[X:%.*]] = getelementptr inbounds [[CLASS_BAR]], ptr [[AGG_TMP]], i64 0, i32 1
; CHECK-NEXT: [[Y:%.*]] = load ptr, ptr [[X]], align 8
; CHECK-NEXT: indirectbr ptr [[PTR]], [label [[BRBLOCK:%.*]], label %B2]
; CHECK: B2:
; CHECK-NEXT: [[B1:%.*]] = bitcast ptr [[Y]] to ptr
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4
; CHECK-NEXT: store i32 [[TMP0]], ptr [[P]], align 4
; CHECK-NEXT: br label [[BRBLOCK]]
; CHECK: BrBlock:
; CHECK-NEXT: [[B2:%.*]] = bitcast ptr [[Y]] to ptr
; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[P]], align 4
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 42
; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]]
; CHECK: T:
; CHECK-NEXT: indirectbr ptr [[P]], [label [[BRBLOCK]], label %B2]
; CHECK: F:
; CHECK-NEXT: indirectbr ptr [[PTR]], [label [[BRBLOCK]], label %B2]
;
entry:
%agg.tmp = alloca %class.bar, align 8
%x= getelementptr inbounds %class.bar, ptr %agg.tmp, i64 0, i32 1
%y = load ptr, ptr %x, align 8
indirectbr ptr %Ptr, [label %BrBlock, label %B2]
B2:
%b1 = bitcast ptr %y to ptr
%0 = load i32, ptr %i, align 4
store i32 %0, ptr %P
br label %BrBlock
BrBlock:
%b2 = bitcast ptr %y to ptr
%L = load i32, ptr %P
%C = icmp eq i32 %L, 42
br i1 %C, label %T, label %F
T:
indirectbr ptr %P, [label %BrBlock, label %B2]
F:
indirectbr ptr %Ptr, [label %BrBlock, label %B2]
}
@_ZTIi = external constant ptr
; Check that an instruction is not hoisted out of landing pad (%lpad4)
; Also within a landing pad no redundancies are removed by gvn-hoist,
; however an instruction may be hoisted into a landing pad if
; landing pad has direct branches (e.g., %lpad to %catch1, %catch)
; This CFG has a cycle (%lpad -> %catch1 -> %lpad4 -> %lpad)
define i32 @foo2(ptr nocapture readonly %i) local_unnamed_addr personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: define i32 @foo2
; CHECK-SAME: (ptr nocapture readonly [[I:%.*]]) local_unnamed_addr personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; CHECK-NEXT: br i1 [[CMP]], label [[TRY_CONT:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then:
; CHECK-NEXT: [[EXCEPTION:%.*]] = tail call ptr @__cxa_allocate_exception(i64 4) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: [[TMP1:%.*]] = bitcast ptr [[EXCEPTION]] to ptr
; CHECK-NEXT: store i32 [[TMP0]], ptr [[TMP1]], align 16
; CHECK-NEXT: invoke void @__cxa_throw(ptr [[EXCEPTION]], ptr @_ZTIi, ptr null) #[[ATTR2:[0-9]+]]
; CHECK-NEXT: to label [[UNREACHABLE:%.*]] unwind label [[LPAD:%.*]]
; CHECK: lpad:
; CHECK-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 }
; CHECK-NEXT: catch ptr @_ZTIi
; CHECK-NEXT: catch ptr null
; CHECK-NEXT: [[BC1:%.*]] = add i32 [[TMP0]], 10
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0
; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 1
; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.eh.typeid.for.p0(ptr @_ZTIi) #[[ATTR1]]
; CHECK-NEXT: [[MATCHES:%.*]] = icmp eq i32 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[BC7:%.*]] = add i32 [[TMP0]], 10
; CHECK-NEXT: [[TMP6:%.*]] = tail call ptr @__cxa_begin_catch(ptr [[TMP3]]) #[[ATTR1]]
; CHECK-NEXT: [[BC4:%.*]] = add i32 [[TMP0]], 10
; CHECK-NEXT: br i1 [[MATCHES]], label [[CATCH1:%.*]], label [[CATCH:%.*]]
; CHECK: catch1:
; CHECK-NEXT: invoke void @__cxa_rethrow() #[[ATTR2]]
; CHECK-NEXT: to label [[UNREACHABLE]] unwind label [[LPAD4:%.*]]
; CHECK: catch:
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1
; CHECK-NEXT: tail call void @__cxa_end_catch()
; CHECK-NEXT: br label [[TRY_CONT]]
; CHECK: lpad4:
; CHECK-NEXT: [[TMP8:%.*]] = landingpad { ptr, i32 }
; CHECK-NEXT: cleanup
; CHECK-NEXT: [[BC5:%.*]] = add i32 [[TMP0]], 10
; CHECK-NEXT: tail call void @__cxa_end_catch() #[[ATTR1]]
; CHECK-NEXT: invoke void @__cxa_throw(ptr [[EXCEPTION]], ptr @_ZTIi, ptr null) #[[ATTR2]]
; CHECK-NEXT: to label [[UNREACHABLE]] unwind label [[LPAD]]
; CHECK: try.cont:
; CHECK-NEXT: [[K_0:%.*]] = phi i32 [ [[ADD]], [[CATCH]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[BC6:%.*]] = add i32 [[TMP0]], 10
; CHECK-NEXT: ret i32 [[K_0]]
; CHECK: unreachable:
; CHECK-NEXT: [[BC2:%.*]] = add i32 [[TMP0]], 10
; CHECK-NEXT: ret i32 [[BC2]]
;
entry:
%0 = load i32, ptr %i, align 4
%cmp = icmp eq i32 %0, 0
br i1 %cmp, label %try.cont, label %if.then
if.then:
%exception = tail call ptr @__cxa_allocate_exception(i64 4) #2
%1 = bitcast ptr %exception to ptr
store i32 %0, ptr %1, align 16
invoke void @__cxa_throw(ptr %exception, ptr @_ZTIi, ptr null) #3
to label %unreachable unwind label %lpad
lpad:
%2 = landingpad { ptr, i32 }
catch ptr @_ZTIi
catch ptr null
%bc1 = add i32 %0, 10
%3 = extractvalue { ptr, i32 } %2, 0
%4 = extractvalue { ptr, i32 } %2, 1
%5 = tail call i32 @llvm.eh.typeid.for.p0(ptr @_ZTIi) #2
%matches = icmp eq i32 %4, %5
%bc7 = add i32 %0, 10
%6 = tail call ptr @__cxa_begin_catch(ptr %3) #2
br i1 %matches, label %catch1, label %catch
catch1:
%bc3 = add i32 %0, 10
invoke void @__cxa_rethrow() #3
to label %unreachable unwind label %lpad4
catch:
%bc4 = add i32 %0, 10
%7 = load i32, ptr %i, align 4
%add = add nsw i32 %7, 1
tail call void @__cxa_end_catch()
br label %try.cont
lpad4:
%8 = landingpad { ptr, i32 }
cleanup
%bc5 = add i32 %0, 10
tail call void @__cxa_end_catch() #2
invoke void @__cxa_throw(ptr %exception, ptr @_ZTIi, ptr null) #3
to label %unreachable unwind label %lpad
try.cont:
%k.0 = phi i32 [ %add, %catch ], [ 0, %entry ]
%bc6 = add i32 %0, 10
ret i32 %k.0
unreachable:
%bc2 = add i32 %0, 10
ret i32 %bc2
}
declare ptr @__cxa_allocate_exception(i64) local_unnamed_addr
declare void @__cxa_throw(ptr, ptr, ptr) local_unnamed_addr
declare i32 @__gxx_personality_v0(...)
; Function Attrs: nounwind readnone
declare i32 @llvm.eh.typeid.for.p0(ptr) #1
declare ptr @__cxa_begin_catch(ptr) local_unnamed_addr
declare void @__cxa_end_catch() local_unnamed_addr
declare void @__cxa_rethrow() local_unnamed_addr
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
attributes #3 = { noreturn }
|
