1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
declare float @llvm.vector.reduce.fadd.f32.v8f32(float, <8 x float>)
declare float @llvm.vector.reduce.fmul.f32.nxv4f32(float, <vscale x 4 x float>)
declare float @llvm.vector.reduce.fmin.f32.v4f32(float, <4 x float>)
declare float @llvm.vector.reduce.fmax.f32.nxv4f32(float, <vscale x 4 x float>)
declare void @use_f32(float)
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
declare i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32>)
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
declare void @use_i32(i32)
declare i32 @llvm.vector.reduce.mul.v4i32(<4 x i32>)
declare i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32>)
declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
declare i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32>)
declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
declare i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32>)
declare <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32>)
declare <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float>)
declare <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32>)
declare <4 x float> @llvm.vector.reverse.v4f32(<4 x float>)
define float @diff_of_sums_v4f32(float %a0, <4 x float> %v0, float %a1, <4 x float> %v1) {
; CHECK-LABEL: @diff_of_sums_v4f32(
; CHECK-NEXT: [[TMP1:%.*]] = fsub reassoc nsz <4 x float> [[V0:%.*]], [[V1:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float [[A0:%.*]], <4 x float> [[TMP1]])
; CHECK-NEXT: [[R:%.*]] = fsub reassoc nsz float [[TMP2]], [[A1:%.*]]
; CHECK-NEXT: ret float [[R]]
;
%r0 = call float @llvm.vector.reduce.fadd.f32.v4f32(float %a0, <4 x float> %v0)
%r1 = call float @llvm.vector.reduce.fadd.f32.v4f32(float %a1, <4 x float> %v1)
%r = fsub reassoc nsz float %r0, %r1
ret float %r
}
define float @reassoc_sum_of_reverse_v4f32(<4 x float> %v0) {
; CHECK-LABEL: @reassoc_sum_of_reverse_v4f32(
; CHECK-NEXT: [[RED:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[V0:%.*]])
; CHECK-NEXT: ret float [[RED]]
;
%rev = call <4 x float> @llvm.vector.reverse.v4f32(<4 x float> %v0)
%red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float zeroinitializer, <4 x float> %rev)
ret float %red
}
define float @reassoc_mul_reduction_of_reverse_nxv4f32(<vscale x 4 x float> %v0) {
; CHECK-LABEL: @reassoc_mul_reduction_of_reverse_nxv4f32(
; CHECK-NEXT: [[RED:%.*]] = call reassoc float @llvm.vector.reduce.fmul.nxv4f32(float 1.000000e+00, <vscale x 4 x float> [[V0:%.*]])
; CHECK-NEXT: ret float [[RED]]
;
%rev = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %v0)
%red = call reassoc float @llvm.vector.reduce.fmul.nxv4f32(float 1.0, <vscale x 4 x float> %rev)
ret float %red
}
define float @fmax_of_reverse_v4f32(<4 x float> %v0) {
; CHECK-LABEL: @fmax_of_reverse_v4f32(
; CHECK-NEXT: [[RED:%.*]] = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[V0:%.*]])
; CHECK-NEXT: ret float [[RED]]
;
%rev = call <4 x float> @llvm.vector.reverse.v4f32(<4 x float> %v0)
%red = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %rev)
ret float %red
}
define float @fmin_of_reverse_nxv4f32(<vscale x 4 x float> %v0) {
; CHECK-LABEL: @fmin_of_reverse_nxv4f32(
; CHECK-NEXT: [[RED:%.*]] = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> [[V0:%.*]])
; CHECK-NEXT: ret float [[RED]]
;
%rev = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %v0)
%red = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %rev)
ret float %red
}
; negative test - fadd cannot be folded with reverse due to lack of reassoc
define float @sum_of_reverse_v4f32(<4 x float> %v0) {
; CHECK-LABEL: @sum_of_reverse_v4f32(
; CHECK-NEXT: [[REV:%.*]] = call <4 x float> @llvm.vector.reverse.v4f32(<4 x float> [[V0:%.*]])
; CHECK-NEXT: [[RED:%.*]] = call float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> [[REV]])
; CHECK-NEXT: ret float [[RED]]
;
%rev = call <4 x float> @llvm.vector.reverse.v4f32(<4 x float> %v0)
%red = call float @llvm.vector.reduce.fadd.v4f32(float zeroinitializer, <4 x float> %rev)
ret float %red
}
; negative test - fmul cannot be folded with reverse due to lack of reassoc
define float @mul_reduction_of_reverse_nxv4f32(<vscale x 4 x float> %v0) {
; CHECK-LABEL: @mul_reduction_of_reverse_nxv4f32(
; CHECK-NEXT: [[REV:%.*]] = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> [[V0:%.*]])
; CHECK-NEXT: [[RED:%.*]] = call float @llvm.vector.reduce.fmul.nxv4f32(float 0.000000e+00, <vscale x 4 x float> [[REV]])
; CHECK-NEXT: ret float [[RED]]
;
%rev = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %v0)
%red = call float @llvm.vector.reduce.fmul.nxv4f32(float zeroinitializer, <vscale x 4 x float> %rev)
ret float %red
}
; negative test - fsub must allow reassociation
define float @diff_of_sums_v4f32_fmf(float %a0, <4 x float> %v0, float %a1, <4 x float> %v1) {
; CHECK-LABEL: @diff_of_sums_v4f32_fmf(
; CHECK-NEXT: [[R0:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[A0:%.*]], <4 x float> [[V0:%.*]])
; CHECK-NEXT: [[R1:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[A1:%.*]], <4 x float> [[V1:%.*]])
; CHECK-NEXT: [[R:%.*]] = fsub nnan ninf nsz float [[R0]], [[R1]]
; CHECK-NEXT: ret float [[R]]
;
%r0 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %a0, <4 x float> %v0)
%r1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %a1, <4 x float> %v1)
%r = fsub ninf nnan nsz float %r0, %r1
ret float %r
}
; negative test - extra uses could create extra instructions
define float @diff_of_sums_extra_use1(float %a0, <4 x float> %v0, float %a1, <4 x float> %v1) {
; CHECK-LABEL: @diff_of_sums_extra_use1(
; CHECK-NEXT: [[R0:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[A0:%.*]], <4 x float> [[V0:%.*]])
; CHECK-NEXT: call void @use_f32(float [[R0]])
; CHECK-NEXT: [[R1:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[A1:%.*]], <4 x float> [[V1:%.*]])
; CHECK-NEXT: [[R:%.*]] = fsub fast float [[R0]], [[R1]]
; CHECK-NEXT: ret float [[R]]
;
%r0 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %a0, <4 x float> %v0)
call void @use_f32(float %r0)
%r1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %a1, <4 x float> %v1)
%r = fsub fast float %r0, %r1
ret float %r
}
; negative test - extra uses could create extra instructions
define float @diff_of_sums_extra_use2(float %a0, <4 x float> %v0, float %a1, <4 x float> %v1) {
; CHECK-LABEL: @diff_of_sums_extra_use2(
; CHECK-NEXT: [[R0:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[A0:%.*]], <4 x float> [[V0:%.*]])
; CHECK-NEXT: [[R1:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[A1:%.*]], <4 x float> [[V1:%.*]])
; CHECK-NEXT: call void @use_f32(float [[R1]])
; CHECK-NEXT: [[R:%.*]] = fsub fast float [[R0]], [[R1]]
; CHECK-NEXT: ret float [[R]]
;
%r0 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %a0, <4 x float> %v0)
%r1 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %a1, <4 x float> %v1)
call void @use_f32(float %r1)
%r = fsub fast float %r0, %r1
ret float %r
}
; negative test - can't reassociate different vector types
define float @diff_of_sums_type_mismatch(float %a0, <4 x float> %v0, float %a1, <8 x float> %v1) {
; CHECK-LABEL: @diff_of_sums_type_mismatch(
; CHECK-NEXT: [[R0:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[A0:%.*]], <4 x float> [[V0:%.*]])
; CHECK-NEXT: [[R1:%.*]] = call fast float @llvm.vector.reduce.fadd.v8f32(float [[A1:%.*]], <8 x float> [[V1:%.*]])
; CHECK-NEXT: [[R:%.*]] = fsub fast float [[R0]], [[R1]]
; CHECK-NEXT: ret float [[R]]
;
%r0 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float %a0, <4 x float> %v0)
%r1 = call fast float @llvm.vector.reduce.fadd.f32.v8f32(float %a1, <8 x float> %v1)
%r = fsub fast float %r0, %r1
ret float %r
}
define i32 @diff_of_sums_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @diff_of_sums_v4i32(
; CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> [[V0:%.*]], [[V1:%.*]]
; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP1]])
; CHECK-NEXT: ret i32 [[R]]
;
%r0 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v0)
%r1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v1)
%r = sub i32 %r0, %r1
ret i32 %r
}
define i32 @sum_of_reverse_v4i32(<4 x i32> %v0) {
; CHECK-LABEL: @sum_of_reverse_v4i32(
; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[V0:%.*]])
; CHECK-NEXT: ret i32 [[RED]]
;
%rev = call <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32> %v0)
%red = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %rev)
ret i32 %red
}
define i32 @sum_of_reverse_nxv4i32(<vscale x 4 x i32> %v0) {
; CHECK-LABEL: @sum_of_reverse_nxv4i32(
; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> [[V0:%.*]])
; CHECK-NEXT: ret i32 [[RED]]
;
%rev = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %v0)
%red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %rev)
ret i32 %red
}
define i32 @mul_reduce_of_reverse_v4i32(<4 x i32> %v0) {
; CHECK-LABEL: @mul_reduce_of_reverse_v4i32(
; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> [[V0:%.*]])
; CHECK-NEXT: ret i32 [[RED]]
;
%rev = call <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32> %v0)
%red = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %rev)
ret i32 %red
}
define i32 @mul_reduce_of_reverse_nxv4i32(<vscale x 4 x i32> %v0) {
; CHECK-LABEL: @mul_reduce_of_reverse_nxv4i32(
; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> [[V0:%.*]])
; CHECK-NEXT: ret i32 [[RED]]
;
%rev = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %v0)
%red = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> %rev)
ret i32 %red
}
define i32 @smin_reduce_of_reverse_v4i32(<4 x i32> %v0) {
; CHECK-LABEL: @smin_reduce_of_reverse_v4i32(
; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> [[V0:%.*]])
; CHECK-NEXT: ret i32 [[RED]]
;
%rev = call <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32> %v0)
%red = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %rev)
ret i32 %red
}
define i32 @smax_reduce_of_reverse_nxv4i32(<vscale x 4 x i32> %v0) {
; CHECK-LABEL: @smax_reduce_of_reverse_nxv4i32(
; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> [[V0:%.*]])
; CHECK-NEXT: ret i32 [[RED]]
;
%rev = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %v0)
%red = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %rev)
ret i32 %red
}
define i32 @umin_reduce_of_reverse_v4i32(<4 x i32> %v0) {
; CHECK-LABEL: @umin_reduce_of_reverse_v4i32(
; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[V0:%.*]])
; CHECK-NEXT: ret i32 [[RED]]
;
%rev = call <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32> %v0)
%red = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %rev)
ret i32 %red
}
define i32 @umax_reduce_of_reverse_nxv4i32(<vscale x 4 x i32> %v0) {
; CHECK-LABEL: @umax_reduce_of_reverse_nxv4i32(
; CHECK-NEXT: [[RED:%.*]] = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> [[V0:%.*]])
; CHECK-NEXT: ret i32 [[RED]]
;
%rev = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %v0)
%red = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %rev)
ret i32 %red
}
; negative test - extra uses could create extra instructions
define i32 @diff_of_sums_v4i32_extra_use1(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @diff_of_sums_v4i32_extra_use1(
; CHECK-NEXT: [[R0:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[V0:%.*]])
; CHECK-NEXT: call void @use_i32(i32 [[R0]])
; CHECK-NEXT: [[R1:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[V1:%.*]])
; CHECK-NEXT: [[R:%.*]] = sub i32 [[R0]], [[R1]]
; CHECK-NEXT: ret i32 [[R]]
;
%r0 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v0)
call void @use_i32(i32 %r0)
%r1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v1)
%r = sub i32 %r0, %r1
ret i32 %r
}
; negative test - extra uses could create extra instructions
define i32 @diff_of_sums_v4i32_extra_use2(<4 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @diff_of_sums_v4i32_extra_use2(
; CHECK-NEXT: [[R0:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[V0:%.*]])
; CHECK-NEXT: [[R1:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[V1:%.*]])
; CHECK-NEXT: call void @use_i32(i32 [[R1]])
; CHECK-NEXT: [[R:%.*]] = sub i32 [[R0]], [[R1]]
; CHECK-NEXT: ret i32 [[R]]
;
%r0 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v0)
%r1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v1)
call void @use_i32(i32 %r1)
%r = sub i32 %r0, %r1
ret i32 %r
}
; negative test - can't reassociate different vector types
define i32 @diff_of_sums_type_mismatch2(<8 x i32> %v0, <4 x i32> %v1) {
; CHECK-LABEL: @diff_of_sums_type_mismatch2(
; CHECK-NEXT: [[R0:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[V0:%.*]])
; CHECK-NEXT: [[R1:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[V1:%.*]])
; CHECK-NEXT: [[R:%.*]] = sub i32 [[R0]], [[R1]]
; CHECK-NEXT: ret i32 [[R]]
;
%r0 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %v0)
%r1 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %v1)
%r = sub i32 %r0, %r1
ret i32 %r
}
|
