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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes="default<O3>" -enable-merge-functions -S < %s | FileCheck %s
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx12.0.0"
define i32 @f(i32 noundef %x) {
; CHECK-LABEL: define range(i32 0, 2) i32 @f(
; CHECK-SAME: i32 noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X]], 8
; CHECK-NEXT: br i1 [[TMP0]], label %[[SWITCH_LOOKUP:.*]], label %[[SW_EPILOG:.*]]
; CHECK: [[SWITCH_LOOKUP]]:
; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[X]] to i64
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], ptr @switch.table.g, i64 0, i64 [[TMP1]]
; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
; CHECK-NEXT: br label %[[SW_EPILOG]]
; CHECK: [[SW_EPILOG]]:
; CHECK-NEXT: [[X_ADDR_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], %[[SWITCH_LOOKUP]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: ret i32 [[X_ADDR_0]]
;
entry:
%x.addr = alloca i32, align 4
store i32 %x, ptr %x.addr, align 4
%0 = load i32, ptr %x.addr, align 4
switch i32 %0, label %sw.default [
i32 0, label %sw.bb
i32 2, label %sw.bb
i32 4, label %sw.bb
i32 6, label %sw.bb
i32 7, label %sw.bb
]
sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
store i32 1, ptr %x.addr, align 4
br label %sw.epilog
sw.default: ; preds = %entry
store i32 0, ptr %x.addr, align 4
br label %sw.epilog
sw.epilog: ; preds = %sw.default, %sw.bb
%1 = load i32, ptr %x.addr, align 4
ret i32 %1
}
define i32 @g(i32 noundef %x) {
; CHECK-LABEL: define range(i32 0, 2) i32 @g(
; CHECK-SAME: i32 noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0]] {
; CHECK-NEXT: [[TMP2:%.*]] = tail call range(i32 0, 2) i32 @f(i32 noundef [[TMP0]]) #[[ATTR0]]
; CHECK-NEXT: ret i32 [[TMP2]]
;
entry:
%x.addr = alloca i32, align 4
store i32 %x, ptr %x.addr, align 4
%0 = load i32, ptr %x.addr, align 4
switch i32 %0, label %sw.default [
i32 0, label %sw.bb
i32 2, label %sw.bb
i32 4, label %sw.bb
i32 6, label %sw.bb
i32 7, label %sw.bb
]
sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
store i32 1, ptr %x.addr, align 4
br label %sw.epilog
sw.default: ; preds = %entry
store i32 0, ptr %x.addr, align 4
br label %sw.epilog
sw.epilog: ; preds = %sw.default, %sw.bb
%1 = load i32, ptr %x.addr, align 4
ret i32 %1
}
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