File: A55-5-mul-sdiv.s

package info (click to toggle)
llvm-toolchain-19 1%3A19.1.7-3
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 1,998,520 kB
  • sloc: cpp: 6,951,680; ansic: 1,486,157; asm: 913,598; python: 232,024; f90: 80,126; objc: 75,281; lisp: 37,276; pascal: 16,990; sh: 10,009; ml: 5,058; perl: 4,724; awk: 3,523; makefile: 3,167; javascript: 2,504; xml: 892; fortran: 664; cs: 573
file content (22 lines) | stat: -rw-r--r-- 773 bytes parent folder | download | duplicates (19) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
 
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views=false --summary-view --iterations=1000 < %s | FileCheck %s

# DIV is not modeled precisely: on hardware it takes variable
# number of cycles depending on its operands. LLVM scheduling model
# only provides an average latency.

add	w8, w8, #1
movz    w10, #1, lsl #16
movz    w12, #32768, lsl #16
mul	w11, w8, w8
sdiv	w10, w12, w10

# CHECK:      Iterations:        1000
# CHECK-NEXT: Instructions:      5000
# CHECK-NEXT: Total Cycles:      8004
# CHECK-NEXT: Total uOps:        5000

# CHECK:      Dispatch Width:    2
# CHECK-NEXT: uOps Per Cycle:    0.62
# CHECK-NEXT: IPC:               0.62
# CHECK-NEXT: Block RThroughput: 8.0