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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s
define amdgpu_gs void @f(i32 inreg %arg, i32 %arg1, i32 %arg2) {
; CHECK-LABEL: f:
; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_cmp_eq_u32 s0, 0
; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: s_cbranch_scc1 .LBB0_2
; CHECK-NEXT: ; %bb.1: ; %bb3
; CHECK-NEXT: v_mov_b32_e32 v5, v0
; CHECK-NEXT: s_branch .LBB0_3
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: v_mov_b32_e32 v5, 1
; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: .LBB0_3: ; %bb4
; CHECK-NEXT: v_mov_b32_e32 v6, 0
; CHECK-NEXT: s_mov_b32 s1, s0
; CHECK-NEXT: s_mov_b32 s2, s0
; CHECK-NEXT: s_mov_b32 s3, s0
; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; CHECK-NEXT: v_mov_b32_e32 v7, v6
; CHECK-NEXT: v_mov_b32_e32 v8, v6
; CHECK-NEXT: v_mov_b32_e32 v2, v6
; CHECK-NEXT: v_mov_b32_e32 v3, v6
; CHECK-NEXT: v_mov_b32_e32 v4, v6
; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: buffer_store_b128 v[5:8], v6, s[0:3], 0 idxen
; CHECK-NEXT: buffer_store_b128 v[1:4], v6, s[0:3], 0 idxen
; CHECK-NEXT: s_nop 0
; CHECK-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; CHECK-NEXT: s_endpgm
bb:
%i = icmp eq i32 %arg, 0
br i1 %i, label %bb4, label %bb3
bb3:
br label %bb4
bb4:
%i5 = phi i32 [ %arg1, %bb3 ], [ 1, %bb ]
%i6 = phi i32 [ %arg2, %bb3 ], [ 0, %bb ]
%i7 = insertelement <4 x i32> zeroinitializer, i32 %i5, i64 0
%i8 = bitcast <4 x i32> %i7 to <4 x float>
call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %i8, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0)
%i9 = insertelement <4 x i32> zeroinitializer, i32 %i6, i64 0
%i10 = bitcast <4 x i32> %i9 to <4 x float>
call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %i10, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0)
ret void
}
declare void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32 immarg)
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