File: cortex-a57-misched-stm-wrback.ll

package info (click to toggle)
llvm-toolchain-19 1%3A19.1.7-3~deb12u1
  • links: PTS, VCS
  • area: main
  • in suites: bookworm-proposed-updates
  • size: 1,998,492 kB
  • sloc: cpp: 6,951,680; ansic: 1,486,157; asm: 913,598; python: 232,024; f90: 80,126; objc: 75,281; lisp: 37,276; pascal: 16,990; sh: 10,009; ml: 5,058; perl: 4,724; awk: 3,523; makefile: 3,167; javascript: 2,504; xml: 892; fortran: 664; cs: 573
file content (35 lines) | stat: -rw-r--r-- 1,067 bytes parent folder | download | duplicates (12) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
 
; REQUIRES: asserts
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; N=3 STMIA_UPD should have latency 2cyc and writeback latency 1cyc

; CHECK:       ********** MI Scheduling **********
; We need second, post-ra scheduling to have STM instruction combined from single-stores
; CHECK:       ********** MI Scheduling **********
; CHECK:       schedule starting
; CHECK:       STMIA_UPD
; CHECK:       rdefs left
; CHECK-NEXT:  Latency            : 2
; CHECK:       Successors
; CHECK:       Data
; CHECK-SAME:  Latency=1

define i32 @bar(i32 %v0, i32 %v1, i32 %v2, ptr %addr) {

  store i32 %v0, ptr %addr

  %addr.2 = getelementptr i32, ptr %addr, i32 1
  store i32 %v1, ptr %addr.2

  %addr.3 = getelementptr i32, ptr %addr, i32 2
  store i32 %v2, ptr %addr.3
  
  %ptr_after = getelementptr i32, ptr %addr, i32 3
  %val = ptrtoint ptr %ptr_after to i32
  
  %rv1 = mul i32 %val, %v0
  %rv2 = mul i32 %rv1, %v1
  %rv3 = mul i32 %rv2, %v2

  ret i32 %rv3
}