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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=arm-pseudo -verify-machineinstrs %s -o - | FileCheck %s
--- |
target triple = "armv7---gnueabi"
define i32 @test1(i32 %x) {
entry:
unreachable
}
define i32 @test2(i32 %x) {
entry:
unreachable
}
define i32 @test3(i32 %x) {
entry:
unreachable
}
define i32 @test4(i32 %x) {
entry:
unreachable
}
@var = global i32 0
define i32 @test5(i32 %x) {
entry:
unreachable
}
...
---
name: test1
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r0
; CHECK-LABEL: name: test1
; CHECK: liveins: $r0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: $r1 = MOVi16 500, 0 /* CC::eq */, killed $cpsr, implicit killed $r1
; CHECK-NEXT: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
$r1 = MOVi 2, 14, $noreg, $noreg
CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
$r1 = MOVCCi16 killed $r1, 500, 0, killed $cpsr
$r0 = MOVr killed $r1, 14, $noreg, $noreg
BX_RET 14, $noreg, implicit $r0
...
---
name: test2
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r0
; CHECK-LABEL: name: test2
; CHECK: liveins: $r0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: $r1 = MOVi16 2068, 0 /* CC::eq */, $cpsr, implicit killed $r1
; CHECK-NEXT: $r1 = MOVTi16 $r1, 7637, 0 /* CC::eq */, $cpsr
; CHECK-NEXT: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
$r1 = MOVi 2, 14, $noreg, $noreg
CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
$r1 = MOVCCi32imm killed $r1, 500500500, 0, killed $cpsr
$r0 = MOVr killed $r1, 14, $noreg, $noreg
BX_RET 14, $noreg, implicit $r0
...
---
name: test3
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r0, $r1
; CHECK-LABEL: name: test3
; CHECK: liveins: $r0, $r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: CMPri $r1, 500, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK-NEXT: $r0 = MOVr killed $r1, 12 /* CC::gt */, killed $cpsr, $noreg, implicit killed $r0
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
CMPri $r1, 500, 14, $noreg, implicit-def $cpsr
$r0 = MOVCCr killed $r0, killed $r1, 12, killed $cpsr
BX_RET 14, $noreg, implicit $r0
...
---
name: test4
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r0_r1', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r0, $r0_r1
; CHECK-LABEL: name: test4
; CHECK: liveins: $r0, $r0_r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r0 = MOVi16 51712, 14 /* CC::al */, $noreg, implicit-def $r0_r1
; CHECK-NEXT: $r0 = MOVTi16 $r0, 15258, 14 /* CC::al */, $noreg, implicit-def $r0_r1
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
$r0 = MOVi32imm 1000000000, implicit-def $r0_r1
BX_RET 14, $noreg, implicit $r0
...
---
name: test5
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r0_r1', virtual-reg: '' }
body: |
bb.0.entry:
liveins: $r0, $r0_r1
; CHECK-LABEL: name: test5
; CHECK: liveins: $r0, $r0_r1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $r0 = MOVi16_ga_pcrel target-flags(arm-lo16) @var, 0, implicit-def $r0_r1
; CHECK-NEXT: $r0 = MOVTi16_ga_pcrel $r0, target-flags(arm-hi16) @var, 0, implicit-def $r0_r1
; CHECK-NEXT: $r0 = PICLDR $r0, 0, 14 /* CC::al */, $noreg, implicit-def $r0_r1
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
$r0 = MOV_ga_pcrel_ldr @var, implicit-def $r0_r1
BX_RET 14, $noreg, implicit $r0
...
|
