1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
define { half, i32 } @test_frexp_f16_i32(half %a) {
; CHECK-LABEL: test_frexp_f16_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: xscvdphp f0, f1
; CHECK-NEXT: addi r4, r1, 44
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: lwz r3, 44(r1)
; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
ret { half, i32 } %result
}
define half @test_frexp_f16_i32_only_use_fract(half %a) {
; CHECK-LABEL: test_frexp_f16_i32_only_use_fract:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: xscvdphp f0, f1
; CHECK-NEXT: addi r4, r1, 44
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
%result.0 = extractvalue { half, i32 } %result, 0
ret half %result.0
}
define i32 @test_frexp_f16_i32_only_use_exp(half %a) {
; CHECK-LABEL: test_frexp_f16_i32_only_use_exp:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: xscvdphp f0, f1
; CHECK-NEXT: addi r4, r1, 44
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: lwz r3, 44(r1)
; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { half, i32 } @llvm.frexp.f16.i32(half %a)
%result.0 = extractvalue { half, i32 } %result, 1
ret i32 %result.0
}
define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
; CHECK-LABEL: test_frexp_v2f16_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r29, -40
; CHECK-NEXT: .cfi_offset r30, -32
; CHECK-NEXT: .cfi_offset f30, -16
; CHECK-NEXT: .cfi_offset f31, -8
; CHECK-NEXT: std r29, -40(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r30, -32(r1) # 8-byte Folded Spill
; CHECK-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
; CHECK-NEXT: stdu r1, -80(r1)
; CHECK-NEXT: std r0, 96(r1)
; CHECK-NEXT: xscvdphp f0, f2
; CHECK-NEXT: addi r30, r1, 32
; CHECK-NEXT: mr r4, r30
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f31, f0
; CHECK-NEXT: xscvdphp f0, f1
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: addi r29, r1, 36
; CHECK-NEXT: fmr f30, f1
; CHECK-NEXT: fmr f1, f31
; CHECK-NEXT: mr r4, r29
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: fmr f2, f1
; CHECK-NEXT: lfiwzx f0, 0, r30
; CHECK-NEXT: lfiwzx f1, 0, r29
; CHECK-NEXT: xxmrghw v2, vs1, vs0
; CHECK-NEXT: fmr f1, f30
; CHECK-NEXT: addi r1, r1, 80
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
; CHECK-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r30, -32(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r29, -40(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
ret { <2 x half>, <2 x i32> } %result
}
define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) {
; CHECK-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset f30, -16
; CHECK-NEXT: .cfi_offset f31, -8
; CHECK-NEXT: stfd f30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
; CHECK-NEXT: stdu r1, -64(r1)
; CHECK-NEXT: std r0, 80(r1)
; CHECK-NEXT: xscvdphp f0, f2
; CHECK-NEXT: addi r4, r1, 40
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f31, f0
; CHECK-NEXT: xscvdphp f0, f1
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: addi r4, r1, 44
; CHECK-NEXT: fmr f30, f1
; CHECK-NEXT: fmr f1, f31
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: fmr f2, f1
; CHECK-NEXT: fmr f1, f30
; CHECK-NEXT: addi r1, r1, 64
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
; CHECK-NEXT: lfd f30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
%result.0 = extractvalue { <2 x half>, <2 x i32> } %result, 0
ret <2 x half> %result.0
}
define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
; CHECK-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: .cfi_offset r29, -32
; CHECK-NEXT: .cfi_offset r30, -24
; CHECK-NEXT: .cfi_offset f31, -8
; CHECK-NEXT: std r29, -32(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r30, -24(r1) # 8-byte Folded Spill
; CHECK-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill
; CHECK-NEXT: stdu r1, -80(r1)
; CHECK-NEXT: std r0, 96(r1)
; CHECK-NEXT: xscvdphp f0, f2
; CHECK-NEXT: addi r30, r1, 40
; CHECK-NEXT: mr r4, r30
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f31, f0
; CHECK-NEXT: xscvdphp f0, f1
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
; CHECK-NEXT: xscvhpdp f1, f0
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: addi r29, r1, 44
; CHECK-NEXT: fmr f1, f31
; CHECK-NEXT: mr r4, r29
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: lfiwzx f0, 0, r30
; CHECK-NEXT: lfiwzx f1, 0, r29
; CHECK-NEXT: xxmrghw v2, vs1, vs0
; CHECK-NEXT: addi r1, r1, 80
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r30, -24(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r29, -32(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
%result.1 = extractvalue { <2 x half>, <2 x i32> } %result, 1
ret <2 x i32> %result.1
}
define { float, i32 } @test_frexp_f32_i32(float %a) {
; CHECK-LABEL: test_frexp_f32_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addi r4, r1, 44
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: lwz r3, 44(r1)
; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
ret { float, i32 } %result
}
define float @test_frexp_f32_i32_only_use_fract(float %a) {
; CHECK-LABEL: test_frexp_f32_i32_only_use_fract:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addi r4, r1, 44
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
%result.0 = extractvalue { float, i32 } %result, 0
ret float %result.0
}
define i32 @test_frexp_f32_i32_only_use_exp(float %a) {
; CHECK-LABEL: test_frexp_f32_i32_only_use_exp:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addi r4, r1, 44
; CHECK-NEXT: bl frexpf
; CHECK-NEXT: nop
; CHECK-NEXT: lwz r3, 44(r1)
; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { float, i32 } @llvm.frexp.f32.i32(float %a)
%result.0 = extractvalue { float, i32 } %result, 1
ret i32 %result.0
}
; FIXME
; define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) {
; %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
; ret { <2 x float>, <2 x i32> } %result
; }
; define <2 x float> @test_frexp_v2f32_v2i32_only_use_fract(<2 x float> %a) {
; %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
; %result.0 = extractvalue { <2 x float>, <2 x i32> } %result, 0
; ret <2 x float> %result.0
; }
; define <2 x i32> @test_frexp_v2f32_v2i32_only_use_exp(<2 x float> %a) {
; %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
; %result.1 = extractvalue { <2 x float>, <2 x i32> } %result, 1
; ret <2 x i32> %result.1
; }
define { double, i32 } @test_frexp_f64_i32(double %a) {
; CHECK-LABEL: test_frexp_f64_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addi r4, r1, 44
; CHECK-NEXT: bl frexp
; CHECK-NEXT: nop
; CHECK-NEXT: lwz r3, 44(r1)
; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { double, i32 } @llvm.frexp.f64.i32(double %a)
ret { double, i32 } %result
}
define double @test_frexp_f64_i32_only_use_fract(double %a) {
; CHECK-LABEL: test_frexp_f64_i32_only_use_fract:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addi r4, r1, 44
; CHECK-NEXT: bl frexp
; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { double, i32 } @llvm.frexp.f64.i32(double %a)
%result.0 = extractvalue { double, i32 } %result, 0
ret double %result.0
}
define i32 @test_frexp_f64_i32_only_use_exp(double %a) {
; CHECK-LABEL: test_frexp_f64_i32_only_use_exp:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: std r0, 64(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: addi r4, r1, 44
; CHECK-NEXT: bl frexp
; CHECK-NEXT: nop
; CHECK-NEXT: lwz r3, 44(r1)
; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call { double, i32 } @llvm.frexp.f64.i32(double %a)
%result.0 = extractvalue { double, i32 } %result, 1
ret i32 %result.0
}
; FIXME: Widen vector result
; define { <2 x double>, <2 x i32> } @test_frexp_v2f64_v2i32(<2 x double> %a) {
; %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
; ret { <2 x double>, <2 x i32> } %result
; }
; define <2 x double> @test_frexp_v2f64_v2i32_only_use_fract(<2 x double> %a) {
; %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
; %result.0 = extractvalue { <2 x double>, <2 x i32> } %result, 0
; ret <2 x double> %result.0
; }
; define <2 x i32> @test_frexp_v2f64_v2i32_only_use_exp(<2 x double> %a) {
; %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
; %result.1 = extractvalue { <2 x double>, <2 x i32> } %result, 1
; ret <2 x i32> %result.1
; }
; FIXME: f128 ExpandFloatResult
; define { ppc_fp128, i32 } @test_frexp_f128_i32(ppc_fp128 %a) {
; %result = call { ppc_fp128, i32 } @llvm.frexp.f128.i32(ppc_fp128 %a)
; ret { ppc_fp128, i32 } %result
; }
; define ppc_fp128 @test_frexp_f128_i32_only_use_fract(ppc_fp128 %a) {
; %result = call { ppc_fp128, i32 } @llvm.frexp.f128.i32(ppc_fp128 %a)
; %result.0 = extractvalue { ppc_fp128, i32 } %result, 0
; ret ppc_fp128 %result.0
; }
; define i32 @test_frexp_f128_i32_only_use_exp(ppc_fp128 %a) {
; %result = call { ppc_fp128, i32 } @llvm.frexp.f128.i32(ppc_fp128 %a)
; %result.0 = extractvalue { ppc_fp128, i32 } %result, 1
; ret i32 %result.0
; }
declare { float, i32 } @llvm.frexp.f32.i32(float) #0
declare { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float>) #0
declare { half, i32 } @llvm.frexp.f16.i32(half) #0
declare { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half>) #0
declare { double, i32 } @llvm.frexp.f64.i32(double) #0
declare { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double>) #0
declare { half, i16 } @llvm.frexp.f16.i16(half) #0
declare { <2 x half>, <2 x i16> } @llvm.frexp.v2f16.v2i16(<2 x half>) #0
declare { ppc_fp128, i32 } @llvm.frexp.f128.i32(ppc_fp128) #0
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
|