1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck %s
define i32 @fcmp_false(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_false:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
%1 = fcmp false bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_oeq(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_oeq:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
; CHECK-NEXT: feq.s a0, fa4, fa5
; CHECK-NEXT: ret
%1 = fcmp oeq bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ogt(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_ogt:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
; CHECK-NEXT: flt.s a0, fa4, fa5
; CHECK-NEXT: ret
%1 = fcmp ogt bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_oge(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_oge:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
; CHECK-NEXT: fle.s a0, fa4, fa5
; CHECK-NEXT: ret
%1 = fcmp oge bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_olt(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_olt:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
; CHECK-NEXT: flt.s a0, fa4, fa5
; CHECK-NEXT: ret
%1 = fcmp olt bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ole(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_ole:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
; CHECK-NEXT: fle.s a0, fa4, fa5
; CHECK-NEXT: ret
%1 = fcmp ole bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_one(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_one:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
; CHECK-NEXT: flt.s a0, fa4, fa5
; CHECK-NEXT: flt.s a1, fa5, fa4
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: ret
%1 = fcmp one bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ord(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_ord:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: feq.s a0, fa5, fa5
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: feq.s a1, fa5, fa5
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: ret
%1 = fcmp ord bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ueq(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_ueq:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
; CHECK-NEXT: flt.s a0, fa4, fa5
; CHECK-NEXT: flt.s a1, fa5, fa4
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp ueq bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ugt(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_ugt:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
; CHECK-NEXT: fle.s a0, fa4, fa5
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp ugt bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_uge(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_uge:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
; CHECK-NEXT: flt.s a0, fa4, fa5
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp uge bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ult(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_ult:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
; CHECK-NEXT: fle.s a0, fa4, fa5
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp ult bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_ule(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_ule:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
; CHECK-NEXT: flt.s a0, fa4, fa5
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp ule bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_une(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_une:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
; CHECK-NEXT: feq.s a0, fa4, fa5
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp une bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_uno(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_uno:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: feq.s a0, fa5, fa5
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: feq.s a1, fa5, fa5
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp uno bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @fcmp_true(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: fcmp_true:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: ret
%1 = fcmp true bfloat %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
}
|
