1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -passes=loop-reduce -S %s | FileCheck %s
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8"
define i32 @btc_0(ptr %a0) {
; CHECK-LABEL: define i32 @btc_0(
; CHECK-SAME: ptr [[A0:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 1, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[V1:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[V8:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[V2:%.*]] = load i32, ptr [[A0]], align 4
; CHECK-NEXT: [[V3:%.*]] = add nsw i32 [[V1]], 1
; CHECK-NEXT: [[V4:%.*]] = srem i32 [[V2]], 3
; CHECK-NEXT: [[V5:%.*]] = icmp ne i32 [[V4]], 0
; CHECK-NEXT: [[V6:%.*]] = sub nsw i32 0, [[V2]]
; CHECK-NEXT: [[V7:%.*]] = select i1 [[V5]], i32 [[V6]], i32 [[V2]]
; CHECK-NEXT: [[V8]] = mul nsw i32 [[V3]], [[V7]]
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 0
; CHECK-NEXT: br i1 [[EC]], label [[B2:%.*]], label [[LOOP]]
; CHECK: b2:
; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[V8]], [[LOOP]] ]
; CHECK-NEXT: br label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret i32 [[RES]]
;
entry:
br label %loop
loop:
%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
%v1 = phi i32 [ 0, %entry ], [ %v8, %loop ]
%v2 = load i32, ptr %a0, align 4
%v3 = add nsw i32 %v1, 1
%v4 = srem i32 %v2, 3
%v5 = icmp ne i32 %v4, 0
%v6 = sub nsw i32 0, %v2
%v7 = select i1 %v5, i32 %v6, i32 %v2
%v8 = mul nsw i32 %v3, %v7
%iv.next = add nsw i32 %iv, 1
%ec = icmp eq i32 %iv.next, 1
br i1 %ec, label %b2, label %loop
b2:
%res = phi i32 [ %v8, %loop ]
br label %exit
exit:
ret i32 %res
}
|
