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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s
; C++ version of test case
; #include <x86intrin.h>
;
; bool allones(__m512i x) {
; return
; x[0] == -1 && x[1] == -1 &&
; x[2] == -1 && x[3] == -1 &&
; x[4] == -1 && x[5] == -1 &&
; x[6] == -1 && x[7] == -1;
; }
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: mustprogress nounwind uwtable
define noundef zeroext i1 @allones(<8 x i64> noundef %x) {
; CHECK-LABEL: @allones(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> [[X:%.*]])
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[TMP0]], -1
; CHECK-NEXT: ret i1 [[TMP1]]
;
entry:
%vecext = extractelement <8 x i64> %x, i32 0
%cmp = icmp eq i64 %vecext, -1
%vecext1 = extractelement <8 x i64> %x, i32 1
%cmp2 = icmp eq i64 %vecext1, -1
%or.cond = select i1 %cmp, i1 %cmp2, i1 false
%vecext4 = extractelement <8 x i64> %x, i32 2
%cmp5 = icmp eq i64 %vecext4, -1
%or.cond20 = select i1 %or.cond, i1 %cmp5, i1 false
%vecext7 = extractelement <8 x i64> %x, i32 3
%cmp8 = icmp eq i64 %vecext7, -1
%or.cond21 = select i1 %or.cond20, i1 %cmp8, i1 false
%vecext10 = extractelement <8 x i64> %x, i32 4
%cmp11 = icmp eq i64 %vecext10, -1
%or.cond22 = select i1 %or.cond21, i1 %cmp11, i1 false
%vecext13 = extractelement <8 x i64> %x, i32 5
%cmp14 = icmp eq i64 %vecext13, -1
%or.cond23 = select i1 %or.cond22, i1 %cmp14, i1 false
%vecext16 = extractelement <8 x i64> %x, i32 6
%cmp17 = icmp eq i64 %vecext16, -1
%or.cond24 = select i1 %or.cond23, i1 %cmp17, i1 false
br i1 %or.cond24, label %land.rhs, label %land.end
land.rhs: ; preds = %entry
%vecext18 = extractelement <8 x i64> %x, i32 7
%cmp19 = icmp eq i64 %vecext18, -1
br label %land.end
land.end: ; preds = %land.rhs, %entry
%0 = phi i1 [ false, %entry ], [ %cmp19, %land.rhs ]
ret i1 %0
}
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