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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=simplifycfg -S | FileCheck %s
declare <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32>, <4 x i32>, i64 immarg)
declare <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32>, i64 immarg)
define <vscale x 4 x i32> @speculate_vector_insert(i32 %c, <4 x i32> %v1, <4 x i32> %v2) {
; CHECK-LABEL: @speculate_vector_insert(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[C:%.*]], 0
; CHECK-NEXT: [[T1:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> zeroinitializer, <4 x i32> [[V1:%.*]], i64 0)
; CHECK-NEXT: [[T2:%.*]] = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> zeroinitializer, <4 x i32> [[V2:%.*]], i64 0)
; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], <vscale x 4 x i32> [[T2]], <vscale x 4 x i32> [[T1]]
; CHECK-NEXT: ret <vscale x 4 x i32> [[COND]]
;
entry:
%tobool = icmp eq i32 %c, 0
br i1 %tobool, label %cond.else, label %cond.then
cond.then: ; preds = %entry
%t1 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> zeroinitializer, <4 x i32> %v1, i64 0)
br label %cond.end
cond.else: ; preds = %entry
%t2 = tail call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> zeroinitializer, <4 x i32> %v2, i64 0)
br label %cond.end
cond.end: ; preds = %cond.else, %cond.then
%cond = phi <vscale x 4 x i32> [ %t1, %cond.then ], [ %t2, %cond.else ]
br label %return
return: ; preds = %cond.end
ret <vscale x 4 x i32> %cond
}
define <4 x i32> @speculate_vector_extract(i32 %c, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2) {
; CHECK-LABEL: @speculate_vector_extract(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[C:%.*]], 0
; CHECK-NEXT: [[T1:%.*]] = tail call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[V1:%.*]], i64 0)
; CHECK-NEXT: [[T2:%.*]] = tail call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> [[V2:%.*]], i64 0)
; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], <4 x i32> [[T2]], <4 x i32> [[T1]]
; CHECK-NEXT: ret <4 x i32> [[COND]]
;
entry:
%tobool = icmp eq i32 %c, 0
br i1 %tobool, label %cond.else, label %cond.then
cond.then: ; preds = %entry
%t1 = tail call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %v1, i64 0)
br label %cond.end
cond.else: ; preds = %entry
%t2 = tail call <4 x i32> @llvm.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %v2, i64 0)
br label %cond.end
cond.end: ; preds = %cond.else, %cond.then
%cond = phi <4 x i32> [ %t1, %cond.then ], [ %t2, %cond.else ]
br label %return
return: ; preds = %cond.end
ret <4 x i32> %cond
}
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