File: issue121601-combine-concat-vectors-assumes-f16.ll

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llvm-toolchain-20 1%3A20.1.6-1~exp1
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s

define <4 x float> @issue121601(bfloat %fptrunc) {
; CHECK-LABEL: issue121601:
; CHECK:       ; %bb.0: ; %bb
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
; CHECK-NEXT:    v_mov_b32_e32 v1, v0
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    v_mov_b32_e32 v3, 0
; CHECK-NEXT:    s_setpc_b64 s[30:31]
bb:
  %bitcast = bitcast bfloat %fptrunc to <1 x bfloat>
  %shufflevector = shufflevector <1 x bfloat> %bitcast, <1 x bfloat> zeroinitializer, <2 x i32> zeroinitializer
  %fpext = fpext <2 x bfloat> %shufflevector to <2 x float>
  %shufflevector1 = shufflevector <2 x float> %fpext, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  ret <4 x float> %shufflevector1
}