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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=armv7-- | FileCheck %s
; Reduced regression test for infinite-loop due to #112710
define void @test(i32 %bf.load.i) {
; CHECK-LABEL: test:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: vldr d16, .LCPI0_0
; CHECK-NEXT: vmov.i64 q9, #0xffff
; CHECK-NEXT: vdup.32 d17, r0
; CHECK-NEXT: vneg.s32 d16, d16
; CHECK-NEXT: vshl.u32 d16, d17, d16
; CHECK-NEXT: vldr d17, .LCPI0_1
; CHECK-NEXT: vand d16, d16, d17
; CHECK-NEXT: vmovl.u32 q8, d16
; CHECK-NEXT: vand q8, q8, q9
; CHECK-NEXT: vst1.64 {d16, d17}, [r0]
; CHECK-NEXT: bl use
; CHECK-NEXT: .p2align 3
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long 8 @ 0x8
; CHECK-NEXT: .long 24 @ 0x18
; CHECK-NEXT: .LCPI0_1:
; CHECK-NEXT: .long 4095 @ 0xfff
; CHECK-NEXT: .long 1 @ 0x1
entry:
%0 = insertelement <2 x i32> poison, i32 %bf.load.i, i64 0
%1 = shufflevector <2 x i32> %0, <2 x i32> poison, <2 x i32> zeroinitializer
%2 = lshr <2 x i32> %1, <i32 8, i32 24>
%arrayinit.element1.i = getelementptr inbounds i8, ptr poison, i32 16
%3 = trunc <2 x i32> %2 to <2 x i16>
%4 = and <2 x i16> %3, <i16 4095, i16 1>
%5 = zext nneg <2 x i16> %4 to <2 x i64>
store <2 x i64> %5, ptr %arrayinit.element1.i, align 8
call void @use()
unreachable
}
declare void @use()
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