1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
|
; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s
; CHECK: v{{[0-9]+}} = vsplat(r{{[0-9]+}})
; CHECK: .comm g0,256,256
; CHECK: .comm g1,128,128
target triple = "hexagon"
@g0 = common global <64 x i32> zeroinitializer, align 256
@g1 = common global <32 x i32> zeroinitializer, align 128
; Function Attrs: nounwind
define i32 @f0() #0 {
b0:
%v0 = alloca i32, align 4
store i32 0, ptr %v0
%v1 = call i32 @f1(i8 zeroext 0)
call void @f2()
%v2 = call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 1)
%v3 = call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 2)
%v4 = call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %v2, <32 x i32> %v3)
%v5 = call <64 x i32> @llvm.hexagon.V6.vtmpyhb.128B(<64 x i32> %v4, i32 12)
store <64 x i32> %v5, ptr @g0, align 256
call void @f3(i32 2048, ptr @g0)
ret i32 0
}
declare i32 @f1(i8 zeroext) #0
declare void @f2(...) #0
; Function Attrs: nounwind readnone
declare <64 x i32> @llvm.hexagon.V6.vtmpyhb.128B(<64 x i32>, i32) #1
; Function Attrs: nounwind readnone
declare <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32>, <32 x i32>) #1
; Function Attrs: nounwind readnone
declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32) #1
declare void @f3(i32, ptr) #0
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
attributes #1 = { nounwind readnone }
|
