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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32 %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64 %s
define void @test1(ptr %a, ptr %b) nounwind {
; RV32-LABEL: test1:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a1, 0(a1)
; RV32-NEXT: lui a2, 524288
; RV32-NEXT: xor a1, a1, a2
; RV32-NEXT: sw a1, 0(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: test1:
; RV64: # %bb.0: # %entry
; RV64-NEXT: lw a1, 0(a1)
; RV64-NEXT: lui a2, 524288
; RV64-NEXT: xor a1, a1, a2
; RV64-NEXT: sw a1, 0(a0)
; RV64-NEXT: ret
entry:
%0 = load float, ptr %b
%neg = fneg float %0
store float %neg, ptr %a
ret void
}
define void @test2(ptr %a, ptr %b) nounwind {
; RV32-LABEL: test2:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 4(a1)
; RV32-NEXT: lw a1, 0(a1)
; RV32-NEXT: lui a3, 524288
; RV32-NEXT: xor a2, a2, a3
; RV32-NEXT: sw a1, 0(a0)
; RV32-NEXT: sw a2, 4(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: test2:
; RV64: # %bb.0: # %entry
; RV64-NEXT: ld a1, 0(a1)
; RV64-NEXT: li a2, -1
; RV64-NEXT: slli a2, a2, 63
; RV64-NEXT: xor a1, a1, a2
; RV64-NEXT: sd a1, 0(a0)
; RV64-NEXT: ret
entry:
%0 = load double, ptr %b
%neg = fneg double %0
store double %neg, ptr %a
ret void
}
define void @test3(ptr %a, ptr %b) nounwind {
; RV32-LABEL: test3:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 12(a1)
; RV32-NEXT: lw a3, 0(a1)
; RV32-NEXT: lw a4, 4(a1)
; RV32-NEXT: lw a1, 8(a1)
; RV32-NEXT: lui a5, 524288
; RV32-NEXT: xor a2, a2, a5
; RV32-NEXT: sw a3, 0(a0)
; RV32-NEXT: sw a4, 4(a0)
; RV32-NEXT: sw a1, 8(a0)
; RV32-NEXT: sw a2, 12(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: test3:
; RV64: # %bb.0: # %entry
; RV64-NEXT: ld a2, 8(a1)
; RV64-NEXT: ld a1, 0(a1)
; RV64-NEXT: li a3, -1
; RV64-NEXT: slli a3, a3, 63
; RV64-NEXT: xor a2, a2, a3
; RV64-NEXT: sd a1, 0(a0)
; RV64-NEXT: sd a2, 8(a0)
; RV64-NEXT: ret
entry:
%0 = load fp128, ptr %b
%neg = fneg fp128 %0
store fp128 %neg, ptr %a
ret void
}
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