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|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin | FileCheck %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin | FileCheck %s
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck %s
; Integers
define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v16i1_v32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vlm.v v8, (a0)
; CHECK-NEXT: li a0, -256
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vadd.vv v11, v9, v9
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vadd.vi v12, v11, -16
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v8, 2
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vadd.vi v11, v11, -15
; CHECK-NEXT: vmerge.vim v13, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0
; CHECK-NEXT: vnsrl.wi v8, v8, 8
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vrgather.vv v10, v13, v12, v0.t
; CHECK-NEXT: vrgather.vv v8, v13, v11, v0.t
; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: ret
%vec = load <32 x i1>, ptr %p
%deinterleaved.results = call {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1> %vec)
%t0 = extractvalue { <16 x i1>, <16 x i1> } %deinterleaved.results, 0
%t1 = extractvalue { <16 x i1>, <16 x i1> } %deinterleaved.results, 1
%res0 = insertvalue { <16 x i1>, <16 x i1> } undef, <16 x i1> %t0, 0
%res1 = insertvalue { <16 x i1>, <16 x i1> } %res0, <16 x i1> %t1, 1
ret {<16 x i1>, <16 x i1>} %res1
}
define {<16 x i8>, <16 x i8>} @vector_deinterleave_load_v16i8_v32i8(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v16i8_v32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vlseg2e8.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <32 x i8>, ptr %p
%deinterleaved.results = call {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8> %vec)
%t0 = extractvalue { <16 x i8>, <16 x i8> } %deinterleaved.results, 0
%t1 = extractvalue { <16 x i8>, <16 x i8> } %deinterleaved.results, 1
%res0 = insertvalue { <16 x i8>, <16 x i8> } undef, <16 x i8> %t0, 0
%res1 = insertvalue { <16 x i8>, <16 x i8> } %res0, <16 x i8> %t1, 1
ret {<16 x i8>, <16 x i8>} %res1
}
; Shouldn't be lowered to vlseg because it's unaligned
define {<8 x i16>, <8 x i16>} @vector_deinterleave_load_v8i16_v16i16_align1(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v8i16_v16i16_align1:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vle8.v v10, (a0)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: vnsrl.wi v9, v10, 16
; CHECK-NEXT: ret
%vec = load <16 x i16>, ptr %p, align 1
%deinterleaved.results = call {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16> %vec)
%t0 = extractvalue { <8 x i16>, <8 x i16> } %deinterleaved.results, 0
%t1 = extractvalue { <8 x i16>, <8 x i16> } %deinterleaved.results, 1
%res0 = insertvalue { <8 x i16>, <8 x i16> } undef, <8 x i16> %t0, 0
%res1 = insertvalue { <8 x i16>, <8 x i16> } %res0, <8 x i16> %t1, 1
ret {<8 x i16>, <8 x i16>} %res1
}
define {<8 x i16>, <8 x i16>} @vector_deinterleave_load_v8i16_v16i16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v8i16_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <16 x i16>, ptr %p
%deinterleaved.results = call {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16> %vec)
%t0 = extractvalue { <8 x i16>, <8 x i16> } %deinterleaved.results, 0
%t1 = extractvalue { <8 x i16>, <8 x i16> } %deinterleaved.results, 1
%res0 = insertvalue { <8 x i16>, <8 x i16> } undef, <8 x i16> %t0, 0
%res1 = insertvalue { <8 x i16>, <8 x i16> } %res0, <8 x i16> %t1, 1
ret {<8 x i16>, <8 x i16>} %res1
}
define {<4 x i32>, <4 x i32>} @vector_deinterleave_load_v4i32_vv8i32(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v4i32_vv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vlseg2e32.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <8 x i32>, ptr %p
%deinterleaved.results = call {<4 x i32>, <4 x i32>} @llvm.vector.deinterleave2.v8i32(<8 x i32> %vec)
%t0 = extractvalue { <4 x i32>, <4 x i32> } %deinterleaved.results, 0
%t1 = extractvalue { <4 x i32>, <4 x i32> } %deinterleaved.results, 1
%res0 = insertvalue { <4 x i32>, <4 x i32> } undef, <4 x i32> %t0, 0
%res1 = insertvalue { <4 x i32>, <4 x i32> } %res0, <4 x i32> %t1, 1
ret {<4 x i32>, <4 x i32>} %res1
}
define {<2 x i64>, <2 x i64>} @vector_deinterleave_load_v2i64_v4i64(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v2i64_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vlseg2e64.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <4 x i64>, ptr %p
%deinterleaved.results = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec)
%t0 = extractvalue { <2 x i64>, <2 x i64> } %deinterleaved.results, 0
%t1 = extractvalue { <2 x i64>, <2 x i64> } %deinterleaved.results, 1
%res0 = insertvalue { <2 x i64>, <2 x i64> } undef, <2 x i64> %t0, 0
%res1 = insertvalue { <2 x i64>, <2 x i64> } %res0, <2 x i64> %t1, 1
ret {<2 x i64>, <2 x i64>} %res1
}
; Floats
define {<2 x bfloat>, <2 x bfloat>} @vector_deinterleave_load_v2bf16_v4bf16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v2bf16_v4bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <4 x bfloat>, ptr %p
%deinterleaved.results = call {<2 x bfloat>, <2 x bfloat>} @llvm.vector.deinterleave2.v4bf16(<4 x bfloat> %vec)
%t0 = extractvalue { <2 x bfloat>, <2 x bfloat> } %deinterleaved.results, 0
%t1 = extractvalue { <2 x bfloat>, <2 x bfloat> } %deinterleaved.results, 1
%res0 = insertvalue { <2 x bfloat>, <2 x bfloat> } undef, <2 x bfloat> %t0, 0
%res1 = insertvalue { <2 x bfloat>, <2 x bfloat> } %res0, <2 x bfloat> %t1, 1
ret {<2 x bfloat>, <2 x bfloat>} %res1
}
define {<4 x bfloat>, <4 x bfloat>} @vector_deinterleave_load_v4bf16_v8bf16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v4bf16_v8bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <8 x bfloat>, ptr %p
%deinterleaved.results = call {<4 x bfloat>, <4 x bfloat>} @llvm.vector.deinterleave2.v8bf16(<8 x bfloat> %vec)
%t0 = extractvalue { <4 x bfloat>, <4 x bfloat> } %deinterleaved.results, 0
%t1 = extractvalue { <4 x bfloat>, <4 x bfloat> } %deinterleaved.results, 1
%res0 = insertvalue { <4 x bfloat>, <4 x bfloat> } undef, <4 x bfloat> %t0, 0
%res1 = insertvalue { <4 x bfloat>, <4 x bfloat> } %res0, <4 x bfloat> %t1, 1
ret {<4 x bfloat>, <4 x bfloat>} %res1
}
define {<2 x half>, <2 x half>} @vector_deinterleave_load_v2f16_v4f16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v2f16_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <4 x half>, ptr %p
%deinterleaved.results = call {<2 x half>, <2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half> %vec)
%t0 = extractvalue { <2 x half>, <2 x half> } %deinterleaved.results, 0
%t1 = extractvalue { <2 x half>, <2 x half> } %deinterleaved.results, 1
%res0 = insertvalue { <2 x half>, <2 x half> } undef, <2 x half> %t0, 0
%res1 = insertvalue { <2 x half>, <2 x half> } %res0, <2 x half> %t1, 1
ret {<2 x half>, <2 x half>} %res1
}
define {<4 x half>, <4 x half>} @vector_deinterleave_load_v4f16_v8f16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v4f16_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <8 x half>, ptr %p
%deinterleaved.results = call {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half> %vec)
%t0 = extractvalue { <4 x half>, <4 x half> } %deinterleaved.results, 0
%t1 = extractvalue { <4 x half>, <4 x half> } %deinterleaved.results, 1
%res0 = insertvalue { <4 x half>, <4 x half> } undef, <4 x half> %t0, 0
%res1 = insertvalue { <4 x half>, <4 x half> } %res0, <4 x half> %t1, 1
ret {<4 x half>, <4 x half>} %res1
}
define {<2 x float>, <2 x float>} @vector_deinterleave_load_v2f32_v4f32(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v2f32_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vlseg2e32.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <4 x float>, ptr %p
%deinterleaved.results = call {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float> %vec)
%t0 = extractvalue { <2 x float>, <2 x float> } %deinterleaved.results, 0
%t1 = extractvalue { <2 x float>, <2 x float> } %deinterleaved.results, 1
%res0 = insertvalue { <2 x float>, <2 x float> } undef, <2 x float> %t0, 0
%res1 = insertvalue { <2 x float>, <2 x float> } %res0, <2 x float> %t1, 1
ret {<2 x float>, <2 x float>} %res1
}
define {<8 x bfloat>, <8 x bfloat>} @vector_deinterleave_load_v8bf16_v16bf16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v8bf16_v16bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <16 x bfloat>, ptr %p
%deinterleaved.results = call {<8 x bfloat>, <8 x bfloat>} @llvm.vector.deinterleave2.v16bf16(<16 x bfloat> %vec)
%t0 = extractvalue { <8 x bfloat>, <8 x bfloat> } %deinterleaved.results, 0
%t1 = extractvalue { <8 x bfloat>, <8 x bfloat> } %deinterleaved.results, 1
%res0 = insertvalue { <8 x bfloat>, <8 x bfloat> } undef, <8 x bfloat> %t0, 0
%res1 = insertvalue { <8 x bfloat>, <8 x bfloat> } %res0, <8 x bfloat> %t1, 1
ret {<8 x bfloat>, <8 x bfloat>} %res1
}
define {<8 x half>, <8 x half>} @vector_deinterleave_load_v8f16_v16f16(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v8f16_v16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vlseg2e16.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <16 x half>, ptr %p
%deinterleaved.results = call {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half> %vec)
%t0 = extractvalue { <8 x half>, <8 x half> } %deinterleaved.results, 0
%t1 = extractvalue { <8 x half>, <8 x half> } %deinterleaved.results, 1
%res0 = insertvalue { <8 x half>, <8 x half> } undef, <8 x half> %t0, 0
%res1 = insertvalue { <8 x half>, <8 x half> } %res0, <8 x half> %t1, 1
ret {<8 x half>, <8 x half>} %res1
}
define {<4 x float>, <4 x float>} @vector_deinterleave_load_v4f32_v8f32(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v4f32_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vlseg2e32.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <8 x float>, ptr %p
%deinterleaved.results = call {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float> %vec)
%t0 = extractvalue { <4 x float>, <4 x float> } %deinterleaved.results, 0
%t1 = extractvalue { <4 x float>, <4 x float> } %deinterleaved.results, 1
%res0 = insertvalue { <4 x float>, <4 x float> } undef, <4 x float> %t0, 0
%res1 = insertvalue { <4 x float>, <4 x float> } %res0, <4 x float> %t1, 1
ret {<4 x float>, <4 x float>} %res1
}
define {<2 x double>, <2 x double>} @vector_deinterleave_load_v2f64_v4f64(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_v2f64_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vlseg2e64.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <4 x double>, ptr %p
%deinterleaved.results = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec)
%t0 = extractvalue { <2 x double>, <2 x double> } %deinterleaved.results, 0
%t1 = extractvalue { <2 x double>, <2 x double> } %deinterleaved.results, 1
%res0 = insertvalue { <2 x double>, <2 x double> } undef, <2 x double> %t0, 0
%res1 = insertvalue { <2 x double>, <2 x double> } %res0, <2 x double> %t1, 1
ret {<2 x double>, <2 x double>} %res1
}
define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @vector_deinterleave_load_factor4(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_factor4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vlseg4e8.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <32 x i8>, ptr %p
%d0 = call {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8> %vec)
%d0.0 = extractvalue { <16 x i8>, <16 x i8> } %d0, 0
%d0.1 = extractvalue { <16 x i8>, <16 x i8> } %d0, 1
%d1 = call {<8 x i8>, <8 x i8>} @llvm.vector.deinterleave2.v16i8(<16 x i8> %d0.0)
%t0 = extractvalue { <8 x i8>, <8 x i8> } %d1, 0
%t2 = extractvalue { <8 x i8>, <8 x i8> } %d1, 1
%d2 = call {<8 x i8>, <8 x i8>} @llvm.vector.deinterleave2.v16i8(<16 x i8> %d0.1)
%t1 = extractvalue { <8 x i8>, <8 x i8> } %d2, 0
%t3 = extractvalue { <8 x i8>, <8 x i8> } %d2, 1
%res0 = insertvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } undef, <8 x i8> %t0, 0
%res1 = insertvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %res0, <8 x i8> %t1, 1
%res2 = insertvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %res1, <8 x i8> %t2, 2
%res3 = insertvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %res2, <8 x i8> %t3, 3
ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %res3
}
define {<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>} @vector_deinterleave_load_factor8(ptr %ptr) {
; CHECK-LABEL: vector_deinterleave_load_factor8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vlseg8e32.v v8, (a0)
; CHECK-NEXT: ret
%vec = load <16 x i32>, ptr %ptr
%d0 = call { <8 x i32>, <8 x i32> } @llvm.vector.deinterleave2.v16i32(<16 x i32> %vec)
%d0.0 = extractvalue { <8 x i32>, <8 x i32> } %d0, 0
%d0.1 = extractvalue { <8 x i32>, <8 x i32> } %d0, 1
%d1 = call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %d0.0)
%d1.0 = extractvalue { <4 x i32>, <4 x i32> } %d1, 0
%d1.1 = extractvalue { <4 x i32>, <4 x i32> } %d1, 1
%d2 = call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %d0.1)
%d2.0 = extractvalue { <4 x i32>, <4 x i32> } %d2, 0
%d2.1 = extractvalue { <4 x i32>, <4 x i32> } %d2, 1
%d3 = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %d1.0)
%t0 = extractvalue { <2 x i32>, <2 x i32> } %d3, 0
%t4 = extractvalue { <2 x i32>, <2 x i32> } %d3, 1
%d4 = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %d1.1)
%t2 = extractvalue { <2 x i32>, <2 x i32> } %d4, 0
%t6 = extractvalue { <2 x i32>, <2 x i32> } %d4, 1
%d5 = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %d2.0)
%t1 = extractvalue { <2 x i32>, <2 x i32> } %d5, 0
%t5 = extractvalue { <2 x i32>, <2 x i32> } %d5, 1
%d6 = call { <2 x i32>, <2 x i32> } @llvm.vector.deinterleave2.v4i32(<4 x i32> %d2.1)
%t3 = extractvalue { <2 x i32>, <2 x i32> } %d6, 0
%t7 = extractvalue { <2 x i32>, <2 x i32> } %d6, 1
%res0 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } undef, <2 x i32> %t0, 0
%res1 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res0, <2 x i32> %t1, 1
%res2 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res1, <2 x i32> %t2, 2
%res3 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res2, <2 x i32> %t3, 3
%res4 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res3, <2 x i32> %t4, 4
%res5 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res4, <2 x i32> %t5, 5
%res6 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res5, <2 x i32> %t6, 6
%res7 = insertvalue { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res6, <2 x i32> %t7, 7
ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %res7
}
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