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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
define <8 x float> @fpext_v8bf16(<8 x bfloat> %x) {
; CHECK-LABEL: fpext_v8bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.w a0, fa0
; CHECK-NEXT: fmv.x.w a1, fa1
; CHECK-NEXT: fmv.x.w a2, fa2
; CHECK-NEXT: fmv.x.w a3, fa3
; CHECK-NEXT: fmv.x.w a4, fa4
; CHECK-NEXT: fmv.x.w a5, fa5
; CHECK-NEXT: fmv.x.w a6, fa6
; CHECK-NEXT: fmv.x.w a7, fa7
; CHECK-NEXT: slli a7, a7, 16
; CHECK-NEXT: slli a6, a6, 16
; CHECK-NEXT: slli a5, a5, 16
; CHECK-NEXT: slli a4, a4, 16
; CHECK-NEXT: slli a3, a3, 16
; CHECK-NEXT: slli a2, a2, 16
; CHECK-NEXT: slli a1, a1, 16
; CHECK-NEXT: slli a0, a0, 16
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.s.x v8, a7
; CHECK-NEXT: vmv.s.x v9, a6
; CHECK-NEXT: vmv.s.x v10, a5
; CHECK-NEXT: vmv.s.x v12, a4
; CHECK-NEXT: vmv.s.x v11, a3
; CHECK-NEXT: vmv.s.x v13, a2
; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv.s.x v14, a1
; CHECK-NEXT: vslideup.vi v12, v10, 1
; CHECK-NEXT: vslideup.vi v13, v11, 1
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vslideup.vi v8, v14, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v12, v9, 2
; CHECK-NEXT: vslideup.vi v8, v13, 2
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v12, 4
; CHECK-NEXT: ret
%y = fpext <8 x bfloat> %x to <8 x float>
ret <8 x float> %y
}
define <8 x float> @fpext_v8f16(<8 x bfloat> %x) {
; CHECK-LABEL: fpext_v8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.w a0, fa0
; CHECK-NEXT: fmv.x.w a1, fa1
; CHECK-NEXT: fmv.x.w a2, fa2
; CHECK-NEXT: fmv.x.w a3, fa3
; CHECK-NEXT: fmv.x.w a4, fa4
; CHECK-NEXT: fmv.x.w a5, fa5
; CHECK-NEXT: fmv.x.w a6, fa6
; CHECK-NEXT: fmv.x.w a7, fa7
; CHECK-NEXT: slli a7, a7, 16
; CHECK-NEXT: slli a6, a6, 16
; CHECK-NEXT: slli a5, a5, 16
; CHECK-NEXT: slli a4, a4, 16
; CHECK-NEXT: slli a3, a3, 16
; CHECK-NEXT: slli a2, a2, 16
; CHECK-NEXT: slli a1, a1, 16
; CHECK-NEXT: slli a0, a0, 16
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.s.x v8, a7
; CHECK-NEXT: vmv.s.x v9, a6
; CHECK-NEXT: vmv.s.x v10, a5
; CHECK-NEXT: vmv.s.x v12, a4
; CHECK-NEXT: vmv.s.x v11, a3
; CHECK-NEXT: vmv.s.x v13, a2
; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmv.s.x v14, a1
; CHECK-NEXT: vslideup.vi v12, v10, 1
; CHECK-NEXT: vslideup.vi v13, v11, 1
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vslideup.vi v8, v14, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v12, v9, 2
; CHECK-NEXT: vslideup.vi v8, v13, 2
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v12, 4
; CHECK-NEXT: ret
%y = fpext <8 x bfloat> %x to <8 x float>
ret <8 x float> %y
}
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