1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --force-dwarf-frame-section %s -o - | FileCheck %s
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
%"struct.std::__va_list" = type { ptr }
define hidden i32 @_Z1fiz(i32 %n, ...) local_unnamed_addr #0 {
; CHECK-LABEL: _Z1fiz:
; CHECK: .cfi_sections .debug_frame
; CHECK-NEXT: .cfi_startproc
; CHECK-NEXT: @ %bb.0: @ %entry
; CHECK-NEXT: pac r12, lr, sp
; CHECK-NEXT: .pad #12
; CHECK-NEXT: sub sp, #12
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: .save {r7, ra_auth_code, lr}
; CHECK-NEXT: push.w {r7, r12, lr}
; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: .cfi_offset lr, -16
; CHECK-NEXT: .cfi_offset ra_auth_code, -20
; CHECK-NEXT: .cfi_offset r7, -24
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .cfi_def_cfa_offset 28
; CHECK-NEXT: add.w r12, sp, #16
; CHECK-NEXT: cmp r0, #1
; CHECK-NEXT: stm.w r12, {r1, r2, r3}
; CHECK-NEXT: add r1, sp, #16
; CHECK-NEXT: str r1, [sp]
; CHECK-NEXT: blt .LBB0_3
; CHECK-NEXT: @ %bb.1: @ %for.body.lr.ph
; CHECK-NEXT: ldr r1, [sp]
; CHECK-NEXT: dls lr, r0
; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: adds r1, #4
; CHECK-NEXT: .LBB0_2: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: str r1, [sp]
; CHECK-NEXT: ldr r2, [r1, #-4]
; CHECK-NEXT: adds r1, #4
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: le lr, .LBB0_2
; CHECK-NEXT: b .LBB0_4
; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: .LBB0_4: @ %for.cond.cleanup
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r7, r12, lr}
; CHECK-NEXT: add sp, #12
; CHECK-NEXT: aut r12, lr, sp
; CHECK-NEXT: bx lr
entry:
%ap = alloca %"struct.std::__va_list", align 4
call void @llvm.va_start(ptr nonnull %ap)
%cmp7 = icmp sgt i32 %n, 0
br i1 %cmp7, label %for.body.lr.ph, label %for.cond.cleanup
for.body.lr.ph: ; preds = %entry
%argp.cur.pre = load ptr, ptr %ap, align 4
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%s.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
call void @llvm.va_end(ptr nonnull %ap)
ret i32 %s.0.lcssa
for.body: ; preds = %for.body.lr.ph, %for.body
%argp.cur = phi ptr [ %argp.cur.pre, %for.body.lr.ph ], [ %argp.next, %for.body ]
%i.09 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
%s.08 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %for.body ]
%argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
store ptr %argp.next, ptr %ap, align 4
%0 = load i32, ptr %argp.cur, align 4
%add = add nsw i32 %0, %s.08
%inc = add nuw nsw i32 %i.09, 1
%exitcond.not = icmp eq i32 %inc, %n
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
}
declare void @llvm.va_start(ptr) #1
declare void @llvm.va_end(ptr) #1
attributes #0 = { nounwind optsize "sign-return-address"="non-leaf" }
attributes #1 = { nounwind "sign-return-address"="non-leaf" }
!llvm.module.flags = !{!0, !1, !2}
!0 = !{i32 8, !"branch-target-enforcement", i32 0}
!1 = !{i32 8, !"sign-return-address", i32 1}
!2 = !{i32 8, !"sign-return-address-all", i32 0}
|
