1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
|
# REQUIRES: aarch64-registered-target
# RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
name: test
body: |
bb.0:
liveins: $x0, $w0
%0:_(s64) = COPY $x0
%1:_(<4 x s16>) = COPY $x0
%2:_(s32) = COPY $w0
; CHECK: *** Bad machine code: G_ASSERT_ZEXT expects an immediate operand #2 ***
; CHECK: instruction: %assert_zext_1:_(s64) = G_ASSERT_ZEXT
%assert_zext_1:_(s64) = G_ASSERT_ZEXT %0, %0
; CHECK: *** Bad machine code: G_ASSERT_ZEXT expects an immediate operand #2 ***
; CHECK: instruction: %assert_zext_2:_(s64) = G_ASSERT_ZEXT
%assert_zext_2:_(s64) = G_ASSERT_ZEXT %0, i8 8
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
; CHECK: instruction: %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT
%assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT %0, 8
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
; CHECK: instruction: %assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT
%assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT %1, 8
; CHECK: *** Bad machine code: G_ASSERT_ZEXT size must be >= 1 ***
; CHECK: instruction: %assert_zext_5:_(s64) = G_ASSERT_ZEXT
%assert_zext_5:_(s64) = G_ASSERT_ZEXT %0, 0
; CHECK: *** Bad machine code: G_ASSERT_ZEXT size must be less than source bit width ***
; CHECK: instruction: %assert_zext_6:_(s64) = G_ASSERT_ZEXT
%assert_zext_6:_(s64) = G_ASSERT_ZEXT %0, 128
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
; CHECK: instruction: %assert_zext_7:_(s64) = G_ASSERT_ZEXT %2:_, 8
%assert_zext_7:_(s64) = G_ASSERT_ZEXT %2, 8
; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***
; CHECK: instruction: %assert_zext_8:_(s64) = G_ASSERT_ZEXT $x0, 8
%assert_zext_8:_(s64) = G_ASSERT_ZEXT $x0, 8
|
