File: ConstraintChecking.inc

package info (click to toggle)
llvm-toolchain-20 1%3A20.1.6-1~exp1
  • links: PTS, VCS
  • area: main
  • in suites: experimental
  • size: 2,111,304 kB
  • sloc: cpp: 7,438,677; ansic: 1,393,822; asm: 1,012,926; python: 241,650; f90: 86,635; objc: 75,479; lisp: 42,144; pascal: 17,286; sh: 10,027; ml: 5,082; perl: 4,730; awk: 3,523; makefile: 3,349; javascript: 2,251; xml: 892; fortran: 672
file content (33 lines) | stat: -rw-r--r-- 874 bytes parent folder | download | duplicates (25)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
include "llvm/Target/Target.td"

def TestTarget : Target;

class Encoding : Instruction {
  field bits<8> Inst;
}

class TestReg<string name, bits<1> enc> : Register<name, []> {
    let HWEncoding{15-1} = 0;
    let HWEncoding{0} = enc;
}

def R0 : TestReg<"R0", 0>;
def R1 : TestReg<"R1", 1>;
def Reg : RegisterClass<"TestTarget", [i32], 32, (sequence "R%d", 0, 1)>;

class TestInstructionWithConstraints<string cstr> : Encoding {
  dag OutOperandList = (outs Reg:$dest1, Reg:$dest2);
  dag InOperandList = (ins Reg:$src1, Reg:$src2);
  string AsmString = "mnemonic $dest1, $dest2, $src1, $src2";
  string AsmVariantName = "";
  let Constraints = cstr;
  field bits<1> dest1;
  field bits<1> dest2;
  field bits<1> src1;
  field bits<1> src2;
  let Inst{7-4} = 0b1010;
  let Inst{3} = dest1{0};
  let Inst{2} = dest2{0};
  let Inst{1} = src1{0};
  let Inst{0} = src2{0};
}