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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux-gnu -mattr=+v < %s | FileCheck %s
define fastcc void @rephase(ptr %phases_in, ptr %157, i64 %158) {
; CHECK-LABEL: define fastcc void @rephase(
; CHECK-SAME: ptr [[PHASES_IN:%.*]], ptr [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[IND_END11:%.*]] = getelementptr i8, ptr [[TMP0]], i64 [[TMP1]]
; CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8
; CHECK-NEXT: [[IMAG_247:%.*]] = getelementptr i8, ptr [[IND_END11]], i64 408
; CHECK-NEXT: [[IMAG_1_251:%.*]] = getelementptr i8, ptr [[IND_END11]], i64 424
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[IMAG_1_251]], align 8
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x double> poison, double [[TMP2]], i32 0
; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[TMP4]], <4 x double> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.vector.insert.v4f64.v2f64(<4 x double> <double 0.000000e+00, double 0.000000e+00, double poison, double poison>, <2 x double> [[TMP3]], i64 2)
; CHECK-NEXT: [[TMP7:%.*]] = fmul <4 x double> [[TMP5]], [[TMP6]]
; CHECK-NEXT: store <4 x double> [[TMP7]], ptr [[IMAG_247]], align 8
; CHECK-NEXT: store double [[TMP2]], ptr [[PHASES_IN]], align 8
; CHECK-NEXT: ret void
;
entry:
%ind.end11 = getelementptr i8, ptr %157, i64 %158
%186 = load double, ptr %157, align 8
%imag.247 = getelementptr i8, ptr %ind.end11, i64 408
%mul35.248 = fmul double %186, 0.000000e+00
store double %mul35.248, ptr %imag.247, align 8
%arrayidx23.1.249 = getelementptr i8, ptr %ind.end11, i64 416
%mul.1.250 = fmul double %186, 0.000000e+00
store double %mul.1.250, ptr %arrayidx23.1.249, align 8
%imag.1.251 = getelementptr i8, ptr %ind.end11, i64 424
%187 = load double, ptr %imag.1.251, align 8
%mul35.1.252 = fmul double %186, %187
store double %mul35.1.252, ptr %imag.1.251, align 8
%arrayidx23.2.253 = getelementptr i8, ptr %ind.end11, i64 432
%188 = load double, ptr %arrayidx23.2.253, align 8
%mul.2.254 = fmul double %186, %188
store double %mul.2.254, ptr %arrayidx23.2.253, align 8
store double %186, ptr %phases_in, align 8
ret void
}
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