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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name: crash_fn
alignment: 4
tracksRegLiveness: true
legalized: true
body: |
bb.1:
; CHECK-LABEL: name: crash_fn
; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[C]](p0) :: (load (s16), align 8)
; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[C]](p0) :: (load (s16))
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ZEXTLOAD1]], [[ZEXTLOAD]]
; CHECK-NEXT: $w0 = COPY [[AND]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:_(p0) = G_CONSTANT i64 0
%6:_(s32) = G_CONSTANT i32 0
%9:_(s1) = G_CONSTANT i1 false
%0:_(s16) = G_LOAD %1(p0) :: (load (s16), align 8)
%2:_(s32) = G_ZEXT %0(s16)
%3:_(s16) = G_LOAD %1(p0) :: (load (s16))
%4:_(s32) = G_ZEXT %3(s16)
%5:_(s32) = G_AND %4, %2
$w0 = COPY %5(s32)
RET_ReallyLR implicit $w0
...
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