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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: test_128_fpr_truncation
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: test_128_fpr_truncation
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (s128))
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRQui]].ssub
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
; CHECK: TBNZW [[COPY2]], 0, %bb.1
; CHECK: bb.1:
; CHECK: RET_ReallyLR
bb.0:
liveins: $x0
%1:gpr(p0) = COPY $x0
%3:gpr(s64) = G_CONSTANT i64 1
%5:gpr(s64) = G_CONSTANT i64 0
%0:fpr(s128) = G_LOAD %1:gpr(p0) :: (load (s128))
%2:fpr(s64) = G_TRUNC %0:fpr(s128)
%8:gpr(s64) = COPY %2:fpr(s64)
%4:gpr(s64) = G_AND %8:gpr, %3:gpr
%7:gpr(s32) = G_ICMP intpred(ne), %4:gpr(s64), %5:gpr
G_BRCOND %7, %bb.1
bb.1:
RET_ReallyLR
...
---
name: no_trunc
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: no_trunc
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (s128))
; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[LDRQui]].dsub
; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]
; CHECK: TBNZX [[COPY2]], 33, %bb.1
; CHECK: bb.1:
; CHECK: RET_ReallyLR
bb.0:
liveins: $x0
%1:gpr(p0) = COPY $x0
%3:gpr(s64) = G_CONSTANT i64 8589934592
%5:gpr(s64) = G_CONSTANT i64 0
%0:fpr(s128) = G_LOAD %1:gpr(p0) :: (load (s128))
%2:fpr(s64) = G_TRUNC %0:fpr(s128)
%8:gpr(s64) = COPY %2:fpr(s64)
%4:gpr(s64) = G_AND %8:gpr, %3:gpr
%7:gpr(s32) = G_ICMP intpred(ne), %4:gpr(s64), %5:gpr
G_BRCOND %7, %bb.1
bb.1:
RET_ReallyLR
|
