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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vreplve.b(<16 x i8>, i32)
define <16 x i8> @lsx_vreplve_b(<16 x i8> %va, i32 %b) nounwind {
; CHECK-LABEL: lsx_vreplve_b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vreplve.b $vr0, $vr0, $a0
; CHECK-NEXT: ret
entry:
%res = call <16 x i8> @llvm.loongarch.lsx.vreplve.b(<16 x i8> %va, i32 %b)
ret <16 x i8> %res
}
declare <8 x i16> @llvm.loongarch.lsx.vreplve.h(<8 x i16>, i32)
define <8 x i16> @lsx_vreplve_h(<8 x i16> %va, i32 %b) nounwind {
; CHECK-LABEL: lsx_vreplve_h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vreplve.h $vr0, $vr0, $a0
; CHECK-NEXT: ret
entry:
%res = call <8 x i16> @llvm.loongarch.lsx.vreplve.h(<8 x i16> %va, i32 %b)
ret <8 x i16> %res
}
declare <4 x i32> @llvm.loongarch.lsx.vreplve.w(<4 x i32>, i32)
define <4 x i32> @lsx_vreplve_w(<4 x i32> %va, i32 %b) nounwind {
; CHECK-LABEL: lsx_vreplve_w:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vreplve.w $vr0, $vr0, $a0
; CHECK-NEXT: ret
entry:
%res = call <4 x i32> @llvm.loongarch.lsx.vreplve.w(<4 x i32> %va, i32 %b)
ret <4 x i32> %res
}
declare <2 x i64> @llvm.loongarch.lsx.vreplve.d(<2 x i64>, i32)
define <2 x i64> @lsx_vreplve_d(<2 x i64> %va, i32 %b) nounwind {
; CHECK-LABEL: lsx_vreplve_d:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vreplve.d $vr0, $vr0, $a0
; CHECK-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vreplve.d(<2 x i64> %va, i32 %b)
ret <2 x i64> %res
}
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