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llvm-toolchain-20 1%3A20.1.8-1~exp1
- links: PTS, VCS
- area: main
- in suites: experimental
- size: 2,111,388 kB
- sloc: cpp: 7,438,767; ansic: 1,393,871; asm: 1,012,926; python: 241,728; f90: 86,635; objc: 75,411; lisp: 42,144; pascal: 17,286; sh: 10,027; ml: 5,082; perl: 4,730; awk: 3,523; makefile: 3,349; javascript: 2,251; xml: 892; fortran: 672
Folder: kernel-name-restriction
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.. (parent) | |||
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d | rwxr-xr-x | 28 | otherdir |
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d | rwxr-xr-x | 83 | some |
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d | rwxr-xr-x | 31 | somedir |
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d | rwxr-xr-x | 69 | uppercase |
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- | rw-r--r-- | 26 | Verilog.cl |
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- | rw-r--r-- | 25 | kernel.cl |
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- | rw-r--r-- | 26 | kernel.h |
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- | rw-r--r-- | 31 | other_Verilog.cl |
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- | rw-r--r-- | 29 | otherthing.cl |
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- | rw-r--r-- | 29 | some_kernel.cl |
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- | rw-r--r-- | 24 | thing.h |
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- | rw-r--r-- | 27 | verilog.h |
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- | rw-r--r-- | 24 | vhdl.CL |
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- | rw-r--r-- | 24 | vhdl.h |
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- | rw-r--r-- | 32 | vhdl_number_two.cl |