1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
|
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
#include <arm_sve.h>
#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif
#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif
// CHECK-LABEL: @test_svqincb_n_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqincb.n32(i32 [[OP:%.*]], i32 31, i32 1)
// CHECK-NEXT: ret i32 [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z18test_svqincb_n_s32i(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqincb.n32(i32 [[OP:%.*]], i32 31, i32 1)
// CPP-CHECK-NEXT: ret i32 [[TMP0]]
//
int32_t test_svqincb_n_s32(int32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svqincb,_n_s32,,)(op, 1);
}
// CHECK-LABEL: @test_svqincb_n_s32_1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqincb.n32(i32 [[OP:%.*]], i32 31, i32 16)
// CHECK-NEXT: ret i32 [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z20test_svqincb_n_s32_1i(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqincb.n32(i32 [[OP:%.*]], i32 31, i32 16)
// CPP-CHECK-NEXT: ret i32 [[TMP0]]
//
int32_t test_svqincb_n_s32_1(int32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svqincb,_n_s32,,)(op, 16);
}
// CHECK-LABEL: @test_svqincb_n_s64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.sqincb.n64(i64 [[OP:%.*]], i32 31, i32 1)
// CHECK-NEXT: ret i64 [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z18test_svqincb_n_s64l(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.sqincb.n64(i64 [[OP:%.*]], i32 31, i32 1)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
int64_t test_svqincb_n_s64(int64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svqincb,_n_s64,,)(op, 1);
}
// CHECK-LABEL: @test_svqincb_n_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.uqincb.n32(i32 [[OP:%.*]], i32 31, i32 16)
// CHECK-NEXT: ret i32 [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z18test_svqincb_n_u32j(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.uqincb.n32(i32 [[OP:%.*]], i32 31, i32 16)
// CPP-CHECK-NEXT: ret i32 [[TMP0]]
//
uint32_t test_svqincb_n_u32(uint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svqincb,_n_u32,,)(op, 16);
}
// CHECK-LABEL: @test_svqincb_n_u64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.uqincb.n64(i64 [[OP:%.*]], i32 31, i32 1)
// CHECK-NEXT: ret i64 [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z18test_svqincb_n_u64m(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.uqincb.n64(i64 [[OP:%.*]], i32 31, i32 1)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svqincb_n_u64(uint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svqincb,_n_u64,,)(op, 1);
}
// CHECK-LABEL: @test_svqincb_pat_n_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqincb.n32(i32 [[OP:%.*]], i32 5, i32 16)
// CHECK-NEXT: ret i32 [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z22test_svqincb_pat_n_s32i(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.sqincb.n32(i32 [[OP:%.*]], i32 5, i32 16)
// CPP-CHECK-NEXT: ret i32 [[TMP0]]
//
int32_t test_svqincb_pat_n_s32(int32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svqincb_pat,_n_s32,,)(op, SV_VL5, 16);
}
// CHECK-LABEL: @test_svqincb_pat_n_s64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.sqincb.n64(i64 [[OP:%.*]], i32 6, i32 1)
// CHECK-NEXT: ret i64 [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z22test_svqincb_pat_n_s64l(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.sqincb.n64(i64 [[OP:%.*]], i32 6, i32 1)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
int64_t test_svqincb_pat_n_s64(int64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svqincb_pat,_n_s64,,)(op, SV_VL6, 1);
}
// CHECK-LABEL: @test_svqincb_pat_n_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.uqincb.n32(i32 [[OP:%.*]], i32 7, i32 16)
// CHECK-NEXT: ret i32 [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z22test_svqincb_pat_n_u32j(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.aarch64.sve.uqincb.n32(i32 [[OP:%.*]], i32 7, i32 16)
// CPP-CHECK-NEXT: ret i32 [[TMP0]]
//
uint32_t test_svqincb_pat_n_u32(uint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svqincb_pat,_n_u32,,)(op, SV_VL7, 16);
}
// CHECK-LABEL: @test_svqincb_pat_n_u64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.uqincb.n64(i64 [[OP:%.*]], i32 8, i32 1)
// CHECK-NEXT: ret i64 [[TMP0]]
//
// CPP-CHECK-LABEL: @_Z22test_svqincb_pat_n_u64m(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.uqincb.n64(i64 [[OP:%.*]], i32 8, i32 1)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svqincb_pat_n_u64(uint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svqincb_pat,_n_u64,,)(op, SV_VL8, 1);
}
|
