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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
# REQUIRES: asserts
# Both the accesses should have an offset of 0
# CHECK: Num BaseOps: 1, Offset: 0, OffsetIsScalable: 0, Width: LocationSize::precise(4)
# CHECK: Num BaseOps: 1, Offset: 0, OffsetIsScalable: 0, Width: LocationSize::precise(4)
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64"
define ptr @post(ptr %p, i32 %d1, i32 %d2) {
entry:
%d3 = mul i32 %d1, %d2
%q = getelementptr i64, ptr %p, i64 3
%r = getelementptr i64, ptr %p, i64 3
store i32 %d3, ptr %p, align 8
%0 = load i32, ptr %r, align 8
store i32 %d1, ptr %p, align 8
%add.ptr = getelementptr inbounds i8, ptr %p, i64 24
ret ptr %add.ptr
}
...
---
name: post
tracksRegLiveness: true
registers:
- { id: 0, class: gpr64common, preferred-register: '' }
- { id: 1, class: gpr32, preferred-register: '' }
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
- { id: 4, class: gpr64common, preferred-register: '' }
liveins:
- { reg: '$x0', virtual-reg: '%0' }
- { reg: '$w1', virtual-reg: '%1' }
- { reg: '$w2', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $x0, $w1, $w2
; CHECK-LABEL: name: post
; CHECK: liveins: $x0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY]], $wzr
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: STRWui [[MADDWrrr]], [[COPY2]], 0 :: (store (s32) into %ir.p, align 8)
; CHECK-NEXT: early-clobber [[COPY2]]:gpr64common = STRWpost [[COPY1]], [[COPY2]], 24 :: (store (s32) into %ir.p, align 8)
; CHECK-NEXT: $x0 = COPY [[COPY2]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%2:gpr32 = COPY $w2
%1:gpr32 = COPY $w1
%4:gpr64common = COPY $x0
%3:gpr32 = MADDWrrr %1, %2, $wzr
STRWui %3, %4, 0 :: (store (s32) into %ir.p, align 8)
early-clobber %4:gpr64common = STRWpost %1, %4, 24 :: (store (s32) into %ir.p, align 8)
$x0 = COPY %4
RET_ReallyLR implicit $x0
...
|
