1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600 %s
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
define amdgpu_kernel void @rotr_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {
; R600-LABEL: rotr_i32:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].Z, KC0[2].W,
;
; SI-LABEL: rotr_i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: v_mov_b32_e32 v0, s3
; SI-NEXT: v_alignbit_b32 v0, s2, s2, v0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; GFX8-LABEL: rotr_i32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s3
; GFX8-NEXT: v_alignbit_b32 v2, s2, s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX10-LABEL: rotr_i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v1, s2, s2, s3
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: rotr_i32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_alignbit_b32 v1, s2, s2, s3
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
entry:
%tmp0 = sub i32 32, %y
%tmp1 = shl i32 %x, %tmp0
%tmp2 = lshr i32 %x, %y
%tmp3 = or i32 %tmp1, %tmp2
store i32 %tmp3, ptr addrspace(1) %in
ret void
}
define amdgpu_kernel void @rotr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {
; R600-LABEL: rotr_v2i32:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].X, KC0[3].Z,
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[2].W, KC0[3].Y,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; SI-LABEL: rotr_v2i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s3
; SI-NEXT: v_alignbit_b32 v1, s1, s1, v0
; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_alignbit_b32 v0, s0, s0, v0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; GFX8-LABEL: rotr_v2i32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s3
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_alignbit_b32 v1, s1, s1, v0
; GFX8-NEXT: v_alignbit_b32 v0, s0, s0, v2
; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm
;
; GFX10-LABEL: rotr_v2i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v1, s1, s1, s3
; GFX10-NEXT: v_alignbit_b32 v0, s0, s0, s2
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: rotr_v2i32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_alignbit_b32 v1, s1, s1, s3
; GFX11-NEXT: v_alignbit_b32 v0, s0, s0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]
; GFX11-NEXT: s_endpgm
entry:
%tmp0 = sub <2 x i32> <i32 32, i32 32>, %y
%tmp1 = shl <2 x i32> %x, %tmp0
%tmp2 = lshr <2 x i32> %x, %y
%tmp3 = or <2 x i32> %tmp1, %tmp2
store <2 x i32> %tmp3, ptr addrspace(1) %in
ret void
}
define amdgpu_kernel void @rotr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {
; R600-LABEL: rotr_v4i32:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[4].X, KC0[5].X,
; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[3].W, KC0[4].W,
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[3].Z, KC0[4].Z,
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[3].Y, KC0[4].Y,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; SI-LABEL: rotr_v4i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s15
; SI-NEXT: v_alignbit_b32 v3, s11, s11, v0
; SI-NEXT: v_mov_b32_e32 v0, s14
; SI-NEXT: v_alignbit_b32 v2, s10, s10, v0
; SI-NEXT: v_mov_b32_e32 v0, s13
; SI-NEXT: v_alignbit_b32 v1, s9, s9, v0
; SI-NEXT: v_mov_b32_e32 v0, s12
; SI-NEXT: v_alignbit_b32 v0, s8, s8, v0
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; GFX8-LABEL: rotr_v4i32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s15
; GFX8-NEXT: v_mov_b32_e32 v1, s14
; GFX8-NEXT: v_mov_b32_e32 v4, s13
; GFX8-NEXT: v_alignbit_b32 v3, s11, s11, v0
; GFX8-NEXT: v_alignbit_b32 v2, s10, s10, v1
; GFX8-NEXT: v_alignbit_b32 v1, s9, s9, v4
; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_alignbit_b32 v0, s8, s8, v0
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
;
; GFX10-LABEL: rotr_v4i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v3, s11, s11, s15
; GFX10-NEXT: v_alignbit_b32 v2, s10, s10, s14
; GFX10-NEXT: v_alignbit_b32 v1, s9, s9, s13
; GFX10-NEXT: v_alignbit_b32 v0, s8, s8, s12
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: rotr_v4i32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: v_mov_b32_e32 v4, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_alignbit_b32 v3, s11, s11, s15
; GFX11-NEXT: v_alignbit_b32 v2, s10, s10, s14
; GFX11-NEXT: v_alignbit_b32 v1, s9, s9, s13
; GFX11-NEXT: v_alignbit_b32 v0, s8, s8, s12
; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-NEXT: s_endpgm
entry:
%tmp0 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
%tmp1 = shl <4 x i32> %x, %tmp0
%tmp2 = lshr <4 x i32> %x, %y
%tmp3 = or <4 x i32> %tmp1, %tmp2
store <4 x i32> %tmp3, ptr addrspace(1) %in
ret void
}
declare i16 @llvm.fshr.i16(i16, i16, i16)
define void @test_rotr_i16(ptr addrspace(1) nocapture readonly %sourceA, ptr addrspace(1) nocapture readonly %sourceB, ptr addrspace(1) nocapture %destValues) {
; R600-LABEL: test_rotr_i16:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
; R600-NEXT: TEX 0 @8
; R600-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]
; R600-NEXT: TEX 0 @10
; R600-NEXT: ALU 21, @14, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT MSKOR T0.XW, T1.X
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: Fetch clause starting at 8:
; R600-NEXT: VTX_READ_16 T0.X, T0.X, 48, #1
; R600-NEXT: Fetch clause starting at 10:
; R600-NEXT: VTX_READ_16 T1.X, T1.X, 32, #1
; R600-NEXT: ALU clause starting at 12:
; R600-NEXT: MOV * T0.X, KC0[2].Z,
; R600-NEXT: ALU clause starting at 13:
; R600-NEXT: MOV * T1.X, KC0[2].Y,
; R600-NEXT: ALU clause starting at 14:
; R600-NEXT: SUB_INT T0.W, 0.0, T0.X,
; R600-NEXT: AND_INT * T1.W, T0.X, literal.x,
; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)
; R600-NEXT: AND_INT * T0.W, PV.W, literal.x,
; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)
; R600-NEXT: LSHL T0.Z, T1.X, PV.W,
; R600-NEXT: LSHR T0.W, T1.X, T1.W,
; R600-NEXT: ADD_INT * T1.W, KC0[2].W, literal.x,
; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00)
; R600-NEXT: AND_INT T2.W, PS, literal.x,
; R600-NEXT: OR_INT * T0.W, PV.W, PV.Z,
; R600-NEXT: 3(4.203895e-45), 0(0.000000e+00)
; R600-NEXT: AND_INT T0.W, PS, literal.x,
; R600-NEXT: LSHL * T2.W, PV.W, literal.y,
; R600-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
; R600-NEXT: LSHL T0.X, PV.W, PS,
; R600-NEXT: LSHL * T0.W, literal.x, PS,
; R600-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
; R600-NEXT: MOV T0.Y, 0.0,
; R600-NEXT: MOV * T0.Z, 0.0,
; R600-NEXT: LSHR * T1.X, T1.W, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; SI-LABEL: test_rotr_i16:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s6
; SI-NEXT: buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:48
; SI-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:32
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v1, 15, v2
; SI-NEXT: v_sub_i32_e32 v2, vcc, 0, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v1, v1, v0
; SI-NEXT: v_and_b32_e32 v2, 15, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, v2, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: buffer_store_short v0, v[4:5], s[4:7], 0 addr64 offset:8
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_rotr_i16:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 32, v0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 48, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GFX8-NEXT: flat_load_ushort v2, v[2:3]
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v0
; GFX8-NEXT: v_sub_u16_e32 v2, 0, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v2, v0
; GFX8-NEXT: v_or_b32_e32 v2, v1, v0
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v4
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_rotr_i16:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: global_load_ushort v6, v[2:3], off offset:48
; GFX10-NEXT: global_load_ushort v7, v[0:1], off offset:32
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_sub_nc_u16 v0, 0, v6
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b16 v1, v6, v7
; GFX10-NEXT: v_lshlrev_b16 v0, v0, v7
; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-NEXT: global_store_short v[4:5], v0, off offset:8
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_rotr_i16:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: global_load_u16 v2, v[2:3], off offset:48
; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:32
; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_sub_nc_u16 v1, 0, v2
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshrrev_b16 v2, v2, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_lshlrev_b16 v0, v1, v0
; GFX11-NEXT: v_or_b32_e32 v0, v2, v0
; GFX11-NEXT: global_store_b16 v[4:5], v0, off offset:8
; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%arrayidx = getelementptr inbounds i16, ptr addrspace(1) %sourceA, i64 16
%a = load i16, ptr addrspace(1) %arrayidx
%arrayidx2 = getelementptr inbounds i16, ptr addrspace(1) %sourceB, i64 24
%b = load i16, ptr addrspace(1) %arrayidx2
%c = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 %b)
%arrayidx5 = getelementptr inbounds i16, ptr addrspace(1) %destValues, i64 4
store i16 %c, ptr addrspace(1) %arrayidx5
ret void
}
|
