File: v6vec-vmemcur-prob.mir

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llvm-toolchain-20 1%3A20.1.8-1~exp1
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# RUN: llc -mtriple=hexagon -start-after if-converter %s -o - | FileCheck %s

# Test that we do no generate a .cur, which refers to vector register generated
# in a previous packet and used in the current packet.

# CHECK-NOT: .cur

---
name: fred
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $r0, $v0, $v1

    $v2 = V6_vaddh $v0, $v1
    $v0 = V6_vL32b_ai $r0, 0
    J2_jumpr $r31, implicit-def $pc, implicit $v0
...