File: get-reg-error-la32.ll

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llvm-toolchain-20 1%3A20.1.8-1~exp1
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not llc < %s --mtriple=loongarch32 -mattr=+d 2>&1 | FileCheck %s

define i64 @read_sp() nounwind {
entry:
; CHECK: On LA32, only 32-bit registers can be read.
  %a1 = call i64 @llvm.read_register.i64(metadata !0)
  ret i64 %a1
}

define void @write_sp(i64 %val) nounwind {
entry:
; CHECK: On LA32, only 32-bit registers can be written.
  call void @llvm.write_register.i64(metadata !0, i64 %val)
  ret void
}

declare i64 @llvm.read_register.i64(metadata) nounwind
declare void @llvm.write_register.i64(metadata, i64) nounwind

!0 = !{!"$sp\00"}